Stephan I. Böttcher
3a0e72eb52
magic.flags, hold_pipe
2026-03-31 14:51:17 +02:00
Stephan I. Böttcher
b6cdc1991f
magic.flags, hold_pipe
2026-03-31 14:45:35 +02:00
Stephan I. Böttcher
f7c1e27d48
uart.py: verbosity
2026-03-31 14:44:44 +02:00
Stephan I. Böttcher
b1356355db
cmd: 'P' fixes
2026-03-31 14:43:40 +02:00
Stephan I. Böttcher
d495bc2db1
python: flash fixes
2026-03-31 09:28:15 +02:00
Stephan I. Böttcher
f839ce7def
fpga_cmd: permit config
2026-03-30 23:49:22 +02:00
Stephan I. Böttcher
4a8a9e3022
fpga config on flash sector boundaries
2026-03-30 23:47:39 +02:00
Stephan I. Böttcher
0f09ed7d13
spi_poll: debugged, can read flash_Id
2026-03-30 18:09:41 +02:00
Stephan I. Böttcher
481c6ce776
spi_poll fixes, comments
2026-03-30 16:12:10 +02:00
Stephan I. Böttcher
be83ec6ff7
config: fpga_config_page
2026-03-30 12:14:14 +02:00
Stephan I. Böttcher
cb60104a10
git_poll: assember implementation
2026-03-30 11:04:13 +02:00
Stephan I. Böttcher
93e1c3230e
main: race free sleep()
2026-03-29 16:02:54 +02:00
Stephan I. Böttcher
66525141bd
cmd: "P" Pipe and "O" fpga confif
2026-03-29 16:01:40 +02:00
Stephan I. Böttcher
36ffd2c4f6
pipe: major development, fixes
2026-03-29 16:00:03 +02:00
Stephan I. Böttcher
6a2f5dc026
fpga_pipe_ready() fix return when not ready
2026-03-29 15:46:53 +02:00
Stephan I. Böttcher
6b668578ea
fpga_start_read() requires configured FPGA
2026-03-29 15:43:10 +02:00
Stephan I. Böttcher
f18e923c96
.gitignore *.s
2026-03-29 10:59:39 +02:00
Stephan I. Böttcher
e63764042f
FPGA: status and pipe support
2026-03-29 10:58:38 +02:00
Stephan I. Böttcher
51d3e09dd3
uart: new inline command_pending()
2026-03-29 10:55:06 +02:00
Stephan I. Böttcher
890aabf955
new inline flash_current_block()
2026-03-29 10:53:32 +02:00
Stephan I. Böttcher
2915785571
TODO comment: speed up spi writes
...
FPGA config takes 5µs per Byte. The ISR could be faster (and shorter)
when the `wdata` is moved to `cmd` after czise and zsize are zero.
2026-03-29 10:48:44 +02:00
Stephan I. Böttcher
b3bb5396de
Makefile: link order
...
The AVR HK packets are basically dumps of the named .bss segments.
The link order defines the layout of those packets. Packet sizes are
16, 32 or 64 bytes. Important things go first, larger packets contain
extra things.
A linker script could define the link order, but we cannot control that
easily.
2026-03-29 10:41:55 +02:00
Stephan I. Böttcher
367479409b
Linker script: fix section overlap
...
Define MEMORY for .eemap and .uumap not overlapping .text.
With more than 4kBytes of flash, the .text segment overlaps
.eemap, .uumap at the real addresses. Add high bits to the
mappings, which are ignored.
The mappings are now ar 0x80xxxx, which is defines for data/RAM,
which must not overlap with anything but .text.
2026-03-29 10:29:44 +02:00
Stephan I. Böttcher
ecc33261a2
dorn: HK calibration and fix of deferred scaled offsets (Vcc→Vss→Vbias)
2026-03-27 17:55:12 +01:00
Stephan I. Böttcher
ea6f1a00d2
py: reduce verbosity of acmd()s
2026-03-27 17:53:43 +01:00
Stephan I. Böttcher
68d335b9ad
HK: bring Vcc into ADC range, R50=15kΩ
2026-03-27 17:53:02 +01:00
Stephan I. Böttcher
8179bdb629
dorn.py: thhor ifc
2026-03-26 22:07:32 +01:00
Stephan I. Böttcher
f94145f233
dorn.py: original copy from irena-arm
2026-03-26 09:53:48 +01:00
Stephan I. Böttcher
c52d619bb7
python: read pressure
2026-03-26 06:16:11 +01:00
Stephan I. Böttcher
6c3ee2ef4f
irena-arm is not usefull
2026-03-25 20:43:22 +01:00
Stephan I. Böttcher
55127a8434
submodules, arm
2026-03-25 20:34:03 +01:00
Stephan I. Böttcher
4c36c00e64
python: fpga commands
2026-03-25 20:25:48 +01:00
Stephan I. Böttcher
a88421a781
avr: fpga_cmd fixes
2026-03-25 20:25:15 +01:00
Stephan I. Böttcher
3f9a100e7c
fpga spi_slave: longer sclk timeout
...
The µC needs about 5 µs between bytes. The 128 mclk timeout @32MHz is
4.3µs. This commit extends the timeout to 1024 mclk cycles.
2026-03-25 20:20:07 +01:00
Stephan I. Böttcher
bc82d2658f
pcb: fix XO53 oscillator enable pin
2026-03-25 20:10:26 +01:00
Stephan I. Böttcher
a4b8e68309
sch: fix XO53 oscillator enable pin
2026-03-25 20:04:14 +01:00
Stephan I. Böttcher
97df4d2a1c
avr: add fpga and pipe
2026-03-25 11:39:24 +01:00
Stephan I. Böttcher
b39371e370
layout: fix soldermask of bottom board frame
2026-03-25 08:12:56 +01:00
Stephan I. Böttcher
9f6f8d342f
update layout image, top and bot in one
2026-03-25 08:08:21 +01:00
Stephan I. Böttcher
f6517860d7
fix pos Vbias HK
...
The offset R for pos Vbias must connect to a negative supply
Use VssH instead of Vadc
Layout Version V2 2026-03-25
Delete stray trace (complained about by Leiton Review)
2026-03-25 07:45:04 +01:00
Stephan I. Böttcher
6dd511a0f5
FSH: 2.7µs gain ×1 and ×15 configuration
2026-03-25 07:37:22 +01:00
11d06b9cc6
Update Electronics features
...
Power Supply, Omnetics, Vbias, Pressure, preamp type
2026-03-25 07:31:22 +01:00
671e1c10ab
Add section and image: Tranformer
2026-03-24 22:22:56 +01:00
606a69bccf
Transformer Image
2026-03-24 22:14:06 +01:00
Stephan I. Böttcher
d8e15f33e0
fix drill diameter of the Omnetics footprint
2026-03-19 14:54:20 +01:00
Stephan I. Böttcher
487b49272e
add bilobe dims to dxf
2026-03-19 13:53:23 +01:00
Stephan I. Böttcher
3866de5c07
fpga/Makefile: iverilog v14
2026-03-18 20:55:59 +01:00
Stephan I. Böttcher
630073928e
Merge branch 'master' of ssh://forge.bexus.org/Stephan/thhor_crs
...
This merges the src/ development (falbala) with the fpga/ development
from etsolo4 and blaulicht.
2026-03-18 11:06:38 +01:00
Stephan I. Böttcher
7bc2c22137
.gitignore thhor.userrow
2026-03-18 10:17:53 +01:00
Stephan I. Böttcher
7e770cbf77
make thhor: fuses and MCU
2026-03-18 10:16:57 +01:00
