Compare commits

...

3 commits

Author SHA1 Message Date
Stephan I. Böttcher
d495bc2db1 python: flash fixes 2026-03-31 09:28:15 +02:00
Stephan I. Böttcher
f839ce7def fpga_cmd: permit config 2026-03-30 23:49:22 +02:00
Stephan I. Böttcher
4a8a9e3022 fpga config on flash sector boundaries 2026-03-30 23:47:39 +02:00
4 changed files with 18 additions and 27 deletions

View file

@ -28,8 +28,8 @@ const struct config config = {
.pwm_max = 0xffff, .pwm_max = 0xffff,
#endif #endif
#ifdef HAVE_FPGA #ifdef HAVE_FPGA
.fpga_config_page = 1, .fpga_config_page = 8,
.fpga_config_count = 511, .fpga_config_count = 504,
#endif #endif
}; };

View file

@ -220,7 +220,7 @@ class dose_cmd(uart.uart):
r.append((dc, self.adc())) r.append((dc, self.adc()))
return r return r
def flash(self, op=None, resp=True, poll=False, **aa): def flash(self, op=None, resp=False, poll=False, **aa):
c = "F" c = "F"
if poll: if poll:
c = "F@" c = "F@"
@ -254,6 +254,7 @@ class dose_cmd(uart.uart):
self.wait_for_spi() self.wait_for_spi()
def wait_for_spi(self): def wait_for_spi(self):
return
while True: while True:
r = self.cmd("F")[1] r = self.cmd("F")[1]
if not r: if not r:
@ -298,10 +299,7 @@ class dose_cmd(uart.uart):
def flash_status(self, blocking=False): def flash_status(self, blocking=False):
r = (0,0,bytes(2)) r = (0,0,bytes(2))
while not r[2][0] & 0x80: while not r[2][0] & 0x80:
self.flash("Status", what="cmdbuf") r = self.flash("Status", resp=True, what="cmdbuf")
r = self.cmd("F<")
while r[1]:
r = self.cmd("F<")
if not blocking: if not blocking:
break break
return tuple(r[2][:2]) return tuple(r[2][:2])
@ -312,10 +310,10 @@ class dose_cmd(uart.uart):
self.flash("Program2", page=page) self.flash("Program2", page=page)
self.flash_status(True) self.flash_status(True)
def write_file2flash(self, page, fn): def write_file2flash(self, page, fn, pages):
n = 0 n = 0
with open(fn, "rb") as f: with open(fn, "rb") as f:
while True: while not pages or n < pages:
b =f.read(512) b =f.read(512)
if not b: if not b:
break break
@ -344,7 +342,7 @@ class dose_cmd(uart.uart):
self.flash(op) self.flash(op)
def flash_Id(self): def flash_Id(self):
r = self.flash("Id", what="cmdbuf") r = self.flash("Id", resp=True, what="cmdbuf")
i = r[2][:5] i = r[2][:5]
print(f"FLASH chip {b2hex(i)}", file=sys.stderr) print(f"FLASH chip {b2hex(i)}", file=sys.stderr)
return i return i
@ -375,7 +373,7 @@ class dose_cmd(uart.uart):
FPGA_FLGS = { FPGA_FLGS = {
"ABORT": 0x01, "ABORT": 0x01,
"ABORTED": 0x10, "DEAD": 0x10,
"BUSY": 0x20, "BUSY": 0x20,
"SUBMITTED": 0x40, "SUBMITTED": 0x40,
"CONFIG": 0x80, "CONFIG": 0x80,

View file

@ -38,21 +38,15 @@ void fpga_cmd(struct fpga_cmd *c)
uint8_t n = c->n; uint8_t n = c->n;
uint8_t z = c->z; uint8_t z = c->z;
if (fpga_status() != as_configured) { if (fpga_status() != as_configured) {
c->n = n | fpga_dead; n |= fpga_dead;
if (~n & fpga_configure) {
c->n = n;
return; return;
} }
if (n & fpga_abort && spi_abort()) {
c->n = n | fpga_aborted;
return;
} }
else if (spi_busy_p()) { c->n = n & ~fpga_busy | fpga_submitted;
c->n = n | fpga_busy;
return;
}
c->n = n & ~fpga_busy;
if (n & fpga_submitted) if (n & fpga_submitted)
return; return;
c->n = n | fpga_submitted;
spi_select(n & fpga_configure ? SPI_CONFIG : 0); spi_select(n & fpga_configure ? SPI_CONFIG : 0);
spi.csize = n &= fpga_size; spi.csize = n &= fpga_size;
@ -62,7 +56,8 @@ void fpga_cmd(struct fpga_cmd *c)
if (z & fpga_wait_nonzero) { if (z & fpga_wait_nonzero) {
spi.isize = n + (z>>3 & fpga_size); // ignore cmd ± (z[6:4]) spi.isize = n + (z>>3 & fpga_size); // ignore cmd ± (z[6:4])
spi.zsize = spi.rsize = z & fpga_size; // read x[3:1] words spi.zsize = spi.rsize = z & fpga_size; // read x[3:1] words
spi.mask = 0xff; // start reading at the first nonzero byte after cmd // start reading at the first byte with MSB set after cmd
spi.mask = spi.wait = 0x80;
} }
else { else {
spi.zsize = z &= 0x7e; // send z zeros/nop after cmd spi.zsize = z &= 0x7e; // send z zeros/nop after cmd

View file

@ -8,13 +8,11 @@ struct fpga_cmd {
}; };
enum fpga_flags { enum fpga_flags {
fpga_abort = 0x01,
fpga_size = 0x0e, fpga_size = 0x0e,
fpga_aborted = 0x10, fpga_dead = 0x10,
fpga_busy = 0x20, fpga_busy = 0x20,
fpga_submitted = 0x40, fpga_submitted = 0x40,
fpga_configure = 0x80, fpga_configure = 0x80,
fpga_dead = 0x80,
fpga_wait_nonzero = 0x01, fpga_wait_nonzero = 0x01,
}; };