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a908ac1c8f
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a908ac1c8f | ||
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00c0cddffe |
8 changed files with 614 additions and 55 deletions
282
fpga/pll.v
Normal file
282
fpga/pll.v
Normal file
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@ -0,0 +1,282 @@
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE.
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// Modified
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`ifndef PLL_LOW_LEVEL
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module pll192
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(
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input inclk0;
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output c0, c1, c2, c3, c4;
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output locked;
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);
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// inclk 12 MHz
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//
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// "192.000000"
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// "96.000000"
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// "64.000000"
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// "32.000000"
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// "16.000000"
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altpll altpll_component
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(
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.inclk ({1'b0, inclk}),
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.clk ({c4, c3, c2, c1, c0}),
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.locked (locked),
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.activeclock (),
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.areset (1'b0),
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.clkbad (),
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.clkena ({6{1'b1}}),
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.clkloss (),
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.clkswitch (1'b0),
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.configupdate (1'b0),
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.enable0 (),
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.enable1 (),
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.extclk (),
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.extclkena ({4{1'b1}}),
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.fbin (1'b1),
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.fbmimicbidir (),
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.fbout (),
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.fref (),
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.icdrclk (),
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.pfdena (1'b1),
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.phasecounterselect ({4{1'b1}}),
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.phasedone (),
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.phasestep (1'b1),
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.phaseupdown (1'b1),
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.pllena (1'b1),
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.scanaclr (1'b0),
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.scanclk (1'b0),
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.scanclkena (1'b1),
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.scandata (1'b0),
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.scandataout (),
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.scandone (),
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.scanread (1'b0),
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.scanwrite (1'b0),
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.sclkout0 (),
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.sclkout1 (),
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.vcooverrange (),
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.vcounderrange ()
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);
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defparam
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altpll_component.bandwidth_type = "AUTO",
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altpll_component.clk0_divide_by = 1,
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altpll_component.clk0_duty_cycle = 50,
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altpll_component.clk0_multiply_by = 16,
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altpll_component.clk0_phase_shift = "0",
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altpll_component.clk1_divide_by = 1,
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altpll_component.clk1_duty_cycle = 50,
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altpll_component.clk1_multiply_by = 8,
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altpll_component.clk1_phase_shift = "2600",
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altpll_component.clk2_divide_by = 3,
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altpll_component.clk2_duty_cycle = 50,
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altpll_component.clk2_multiply_by = 16,
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altpll_component.clk2_phase_shift = "0",
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altpll_component.clk3_divide_by = 3,
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altpll_component.clk3_duty_cycle = 50,
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altpll_component.clk3_multiply_by = 8,
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altpll_component.clk3_phase_shift = "7800",
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altpll_component.clk4_divide_by = 3,
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altpll_component.clk4_duty_cycle = 50,
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altpll_component.clk4_multiply_by = 4,
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altpll_component.clk4_phase_shift = "23440",
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 83333,
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altpll_component.intended_device_family = "Cyclone 10 LP",
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altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll192",
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altpll_component.lpm_type = "altpll",
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altpll_component.operation_mode = "NORMAL",
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altpll_component.pll_type = "AUTO",
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altpll_component.port_activeclock = "PORT_UNUSED",
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altpll_component.port_areset = "PORT_UNUSED",
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altpll_component.port_clkbad0 = "PORT_UNUSED",
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altpll_component.port_clkbad1 = "PORT_UNUSED",
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altpll_component.port_clkloss = "PORT_UNUSED",
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altpll_component.port_clkswitch = "PORT_UNUSED",
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altpll_component.port_configupdate = "PORT_UNUSED",
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altpll_component.port_fbin = "PORT_UNUSED",
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altpll_component.port_inclk0 = "PORT_USED",
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altpll_component.port_inclk1 = "PORT_UNUSED",
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altpll_component.port_locked = "PORT_USED",
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altpll_component.port_pfdena = "PORT_UNUSED",
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altpll_component.port_phasecounterselect = "PORT_UNUSED",
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altpll_component.port_phasedone = "PORT_UNUSED",
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altpll_component.port_phasestep = "PORT_UNUSED",
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altpll_component.port_phaseupdown = "PORT_UNUSED",
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altpll_component.port_pllena = "PORT_UNUSED",
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altpll_component.port_scanaclr = "PORT_UNUSED",
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altpll_component.port_scanclk = "PORT_UNUSED",
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altpll_component.port_scanclkena = "PORT_UNUSED",
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altpll_component.port_scandata = "PORT_UNUSED",
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altpll_component.port_scandataout = "PORT_UNUSED",
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altpll_component.port_scandone = "PORT_UNUSED",
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altpll_component.port_scanread = "PORT_UNUSED",
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altpll_component.port_scanwrite = "PORT_UNUSED",
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altpll_component.port_clk0 = "PORT_USED",
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altpll_component.port_clk1 = "PORT_USED",
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altpll_component.port_clk2 = "PORT_USED",
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altpll_component.port_clk3 = "PORT_USED",
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altpll_component.port_clk4 = "PORT_USED",
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altpll_component.port_clk5 = "PORT_UNUSED",
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altpll_component.port_clkena0 = "PORT_UNUSED",
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altpll_component.port_clkena1 = "PORT_UNUSED",
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altpll_component.port_clkena2 = "PORT_UNUSED",
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altpll_component.port_clkena3 = "PORT_UNUSED",
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altpll_component.port_clkena4 = "PORT_UNUSED",
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altpll_component.port_clkena5 = "PORT_UNUSED",
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altpll_component.port_extclk0 = "PORT_UNUSED",
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altpll_component.port_extclk1 = "PORT_UNUSED",
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altpll_component.port_extclk2 = "PORT_UNUSED",
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altpll_component.port_extclk3 = "PORT_UNUSED",
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altpll_component.self_reset_on_loss_lock = "OFF",
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altpll_component.width_clock = 5;
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endmodule
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`else // !`ifdef PLL_LOW_LEVEL
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module pll192
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(
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input inclk0;
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output c0, c1, c2, c3, c4;
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output locked;
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);
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altpll altpll_component
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(
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.inclk ({1'b0, inclk}),
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.clk ({c4, c3, c2, c1, c0}),
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.locked (locked),
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.activeclock (),
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.areset (1'b0),
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.clkbad (),
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.clkena ({6{1'b1}}),
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.clkloss (),
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.clkswitch (1'b0),
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.configupdate (1'b0),
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.enable0 (),
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.enable1 (),
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.extclk (),
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.extclkena ({4{1'b1}}),
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.fbin (1'b1),
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.fbmimicbidir (),
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.fbout (),
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.fref (),
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.icdrclk (),
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.pfdena (1'b1),
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.phasecounterselect ({4{1'b1}}),
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.phasedone (),
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.phasestep (1'b1),
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.phaseupdown (1'b1),
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.pllena (1'b1),
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.scanaclr (1'b0),
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.scanclk (1'b0),
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.scanclkena (1'b1),
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.scandata (1'b0),
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.scandataout (),
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.scandone (),
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.scanread (1'b0),
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.scanwrite (1'b0),
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.sclkout0 (),
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.sclkout1 (),
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.vcooverrange (),
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.vcounderrange ()
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);
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defparam
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altpll_component.charge_pump_current_bits = 1,
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 83333,
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`ifdef CYCLONE10
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altpll_component.intended_device_family = "Cyclone 10 LP",
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`endif
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altpll_component.loop_filter_c_bits = 0,
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altpll_component.loop_filter_r_bits = 24,
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altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll192",
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altpll_component.lpm_type = "altpll",
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altpll_component.m = 32,
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altpll_component.m_initial = 1,
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altpll_component.m_ph = 0,
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altpll_component.n = 1,
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altpll_component.operation_mode = "NORMAL",
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altpll_component.pll_type = "AUTO",
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altpll_component.port_activeclock = "PORT_UNUSED",
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altpll_component.port_areset = "PORT_UNUSED",
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altpll_component.port_clkbad0 = "PORT_UNUSED",
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altpll_component.port_clkbad1 = "PORT_UNUSED",
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altpll_component.port_clkloss = "PORT_UNUSED",
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altpll_component.port_clkswitch = "PORT_UNUSED",
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altpll_component.port_configupdate = "PORT_UNUSED",
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altpll_component.port_fbin = "PORT_UNUSED",
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altpll_component.port_inclk0 = "PORT_USED",
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altpll_component.port_inclk1 = "PORT_UNUSED",
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altpll_component.port_locked = "PORT_USED",
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altpll_component.port_pfdena = "PORT_UNUSED",
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altpll_component.port_phasecounterselect = "PORT_UNUSED",
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altpll_component.port_phasedone = "PORT_UNUSED",
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altpll_component.port_phasestep = "PORT_UNUSED",
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altpll_component.port_phaseupdown = "PORT_UNUSED",
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altpll_component.port_pllena = "PORT_UNUSED",
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altpll_component.port_scanaclr = "PORT_UNUSED",
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altpll_component.port_scanclk = "PORT_UNUSED",
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altpll_component.port_scanclkena = "PORT_UNUSED",
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altpll_component.port_scandata = "PORT_UNUSED",
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altpll_component.port_scandataout = "PORT_UNUSED",
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altpll_component.port_scandone = "PORT_UNUSED",
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altpll_component.port_scanread = "PORT_UNUSED",
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altpll_component.port_scanwrite = "PORT_UNUSED",
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altpll_component.port_clk0 = "PORT_USED",
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altpll_component.port_clk1 = "PORT_USED",
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altpll_component.port_clk2 = "PORT_USED",
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altpll_component.port_clk3 = "PORT_USED",
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altpll_component.port_clk4 = "PORT_USED",
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altpll_component.port_clk5 = "PORT_UNUSED",
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altpll_component.port_clkena0 = "PORT_UNUSED",
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altpll_component.port_clkena1 = "PORT_UNUSED",
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altpll_component.port_clkena2 = "PORT_UNUSED",
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altpll_component.port_clkena3 = "PORT_UNUSED",
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altpll_component.port_clkena4 = "PORT_UNUSED",
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altpll_component.port_clkena5 = "PORT_UNUSED",
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altpll_component.port_extclk0 = "PORT_UNUSED",
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altpll_component.port_extclk1 = "PORT_UNUSED",
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altpll_component.port_extclk2 = "PORT_UNUSED",
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altpll_component.port_extclk3 = "PORT_UNUSED",
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altpll_component.self_reset_on_loss_lock = "OFF",
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altpll_component.vco_post_scale = 2,
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altpll_component.width_clock = 5,
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altpll_component.c0_high = 1,
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altpll_component.c0_initial = 1,
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altpll_component.c0_low = 1,
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altpll_component.c0_mode = "even",
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altpll_component.c0_ph = 0,
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altpll_component.c1_high = 2,
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altpll_component.c1_initial = 2,
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altpll_component.c1_low = 2,
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altpll_component.c1_mode = "even",
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altpll_component.c1_ph = 0,
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altpll_component.c2_high = 3,
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altpll_component.c2_initial = 1,
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altpll_component.c2_low = 3,
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altpll_component.c2_mode = "even",
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altpll_component.c2_ph = 0,
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altpll_component.c3_high = 6,
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altpll_component.c3_initial = 4,
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altpll_component.c3_low = 6,
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altpll_component.c3_mode = "even",
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altpll_component.c3_ph = 0,
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altpll_component.c4_high = 12,
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altpll_component.c4_initial = 10,
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altpll_component.c4_low = 12,
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altpll_component.c4_mode = "even",
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altpll_component.c4_ph = 0,
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altpll_component.clk0_counter = "c0",
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altpll_component.clk1_counter = "c1",
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altpll_component.clk2_counter = "c2",
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altpll_component.clk3_counter = "c3",
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altpll_component.clk4_counter = "c4";
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endmodule
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`endif // !`ifdef PLL_LOW_LEVEL
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31
fpga/thhor_crs.qpf
Normal file
31
fpga/thhor_crs.qpf
Normal file
|
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@ -0,0 +1,31 @@
|
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# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
# Date created = 15:55:15 January 24, 2024
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
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QUARTUS_VERSION = "20.1"
|
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DATE = "15:55:15 January 24, 2024"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "thhor_crs"
|
||||
207
fpga/thhor_crs.qsf
Normal file
207
fpga/thhor_crs.qsf
Normal file
|
|
@ -0,0 +1,207 @@
|
|||
# -*- tcl -*-
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# irena_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY quartus
|
||||
|
||||
set_global_assignment -name DEVICE 10CL025YE144I7G
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY thhor_crs
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
|
||||
set_global_assignment -name MISC_FILE thhor_crs.dpf
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
||||
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name CRC_ERROR_CHECKING ON
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO OFF
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
|
||||
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
|
||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "Custom Verilog HDL"
|
||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
|
||||
set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
|
||||
############ Left 3.3V
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to xclk
|
||||
set_location_assignment PIN_22 -to xclk
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_ssel
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_sck
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_mosi
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_miso
|
||||
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to spi_ssel
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to spi_miso
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to spi_mosi
|
||||
|
||||
set_location_assignment PIN_8 -to spi_ssel
|
||||
set_location_assignment PIN_11 -to spi_sck
|
||||
set_location_assignment PIN_12 -to spi_mosi
|
||||
set_location_assignment PIN_10 -to spi_miso
|
||||
|
||||
############# right 2.5V
|
||||
|
||||
# LVDS spacewire
|
||||
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to S_OUT
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to D_OUT
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to S_IN
|
||||
set_instance_assignment -name IO_STANDARD LVDS -to D_IN
|
||||
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to S_OUT
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to D_OUT
|
||||
|
||||
set_location_assignment PIN_87 -to S_OUT
|
||||
set_location_assignment PIN_86 -to "S_OUT(n)"
|
||||
set_location_assignment PIN_103 -to D_OUT
|
||||
set_location_assignment PIN_101 -to "D_OUT(n)"
|
||||
set_location_assignment PIN_91 -to S_IN
|
||||
set_location_assignment PIN_60 -to "S_IN(n)"
|
||||
|
||||
# Pressure Sensor
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_Dout
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_Din
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_MCLK
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to pt_SCLK
|
||||
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_Din
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to pt_Dout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_MCLK
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pt_SCLK
|
||||
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to pt_DOUT
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_Din
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_MCLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "8mA" -to pt_SCLK
|
||||
|
||||
set_instance_assignment -name SLEW_RATE 0 -to pt_Din
|
||||
set_instance_assignment -name SLEW_RATE 0 -to pt_MCLK
|
||||
set_instance_assignment -name SLEW_RATE 0 -to pt_SCLK
|
||||
|
||||
set_location_assignment PIN_77 -to pt_Dout
|
||||
set_location_assignment PIN_80 -to pt_Din
|
||||
set_location_assignment PIN_83 -to pt_MCLK
|
||||
set_location_assignment PIN_76 -to pt_SCLK
|
||||
|
||||
########## bottom 3.3V
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_nCS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_DIN
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to ADC_DOUT
|
||||
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_SCK
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to ADC_DIN
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to ADC_DOUT
|
||||
|
||||
set_location_assignment PIN_66 -to ADC_nCS[0]
|
||||
set_location_assignment PIN_69 -to ADC_SCK[0]
|
||||
set_location_assignment PIN_67 -to ADC_DIN[0]
|
||||
set_location_assignment PIN_68 -to ADC_DOUT[0]
|
||||
|
||||
set_location_assignment PIN_58 -to ADC_nCS[1]
|
||||
set_location_assignment PIN_65 -to ADC_SCK[1]
|
||||
set_location_assignment PIN_59 -to ADC_DIN[1]
|
||||
set_location_assignment PIN_60 -to ADC_DOUT[1]
|
||||
|
||||
set_location_assignment PIN_46 -to ADC_nCS[2]
|
||||
set_location_assignment PIN_51 -to ADC_SCK[2]
|
||||
set_location_assignment PIN_49 -to ADC_DIN[2]
|
||||
set_location_assignment PIN_50 -to ADC_DOUT[2]
|
||||
|
||||
set_location_assignment PIN_39 -to ADC_nCS[3]
|
||||
set_location_assignment PIN_44 -to ADC_SCK[3]
|
||||
set_location_assignment PIN_42 -to ADC_DIN[3]
|
||||
set_location_assignment PIN_43 -to ADC_DOUT[3]
|
||||
|
||||
########## Spares 3.3V left, top
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to P33
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to P33
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to P33
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to P33
|
||||
|
||||
set_location_assignment PIN_6 -to P33[0]
|
||||
set_location_assignment PIN_7 -to P33[1]
|
||||
set_location_assignment PIN_28 -to P33[2]
|
||||
set_location_assignment PIN_31 -to P33[3]
|
||||
set_location_assignment PIN_32 -to P33[4]
|
||||
set_location_assignment PIN_33 -to P33[5]
|
||||
set_location_assignment PIN_71 -to P33[6]
|
||||
set_location_assignment PIN_72 -to P33[7]
|
||||
|
||||
|
||||
########## Spares 2.5V right, bottom
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "2.5 V" -to P25
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to P25
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to P25
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to P25
|
||||
|
||||
set_location_assignment PIN_105 -to P25[0]
|
||||
set_location_assignment PIN_106 -to P25[1]
|
||||
set_location_assignment PIN_111 -to P25[2]
|
||||
set_location_assignment PIN_112 -to P25[3]
|
||||
set_location_assignment PIN_113 -to P25[4]
|
||||
set_location_assignment PIN_114 -to P25[5]
|
||||
set_location_assignment PIN_115 -to P25[6]
|
||||
set_location_assignment PIN_119 -to P25[7]
|
||||
set_location_assignment PIN_120 -to P25[8]
|
||||
set_location_assignment PIN_121 -to P25[9]
|
||||
set_location_assignment PIN_125 -to P25[10]
|
||||
set_location_assignment PIN_132 -to P25[11]
|
||||
set_location_assignment PIN_133 -to P25[12]
|
||||
set_location_assignment PIN_135 -to P25[13]
|
||||
set_location_assignment PIN_136 -to P25[14]
|
||||
set_location_assignment PIN_137 -to P25[15]
|
||||
set_location_assignment PIN_141 -to P25[16]
|
||||
set_location_assignment PIN_142 -to P25[17]
|
||||
set_location_assignment PIN_143 -to P25[18]
|
||||
set_location_assignment PIN_144 -to P25[19]
|
||||
|
||||
########## Sources
|
||||
|
||||
set_global_assignment -name VERILOG_FILE thhor_crs.v
|
||||
set_global_assignment -name VERILOG_FILE pll.v
|
||||
|
||||
set_global_assignment -name VERILOG_MACRO "TARGET_ALTERA=1"
|
||||
set_global_assignment -name VERILOG_MACRO "TARGET_10C25=1"
|
||||
set_global_assignment -name VERILOG_MACRO "INFERRED_SRAM=1"
|
||||
|
||||
7
fpga/thhor_crs.sdc
Normal file
7
fpga/thhor_crs.sdc
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
create_clock -name xclk -period 83.333 xclk
|
||||
derive_pll_clocks
|
||||
derive_clock_uncertainty
|
||||
set_false_path -from spi_sck -to xclk
|
||||
set_false_path -from xclk -to spi_sck
|
||||
set_false_path -from spi_sck -to {pll0|altpll_component|auto_generated|pll1|clk[3]}
|
||||
set_false_path -from {pll0|altpll_component|auto_generated|pll1|clk[3]} -to spi_sck
|
||||
32
fpga/thhor_crs.v
Normal file
32
fpga/thhor_crs.v
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
|
||||
module thhor_crs
|
||||
(
|
||||
input xclk,
|
||||
input spi_ssel, spi_sck, spi_mosi,
|
||||
output spi_miso,
|
||||
|
||||
// Barometer
|
||||
output pt_MCLK, pt_SCLK, pt_Din,
|
||||
input pt_Dout,
|
||||
|
||||
// ADCs
|
||||
output [3:0] ADC_nCS, ADC_SCK, ADC_DIN,
|
||||
input [3:0] ADC_DOUT,
|
||||
|
||||
// LVDS
|
||||
output S_OUT, D_OUT,
|
||||
input S_IN, D_IN,
|
||||
|
||||
// Spare Pins
|
||||
inout [19:0] P25,
|
||||
inout [7:0] P33,
|
||||
);
|
||||
|
||||
wire pll_locked;
|
||||
wire mclk;
|
||||
pll192 pll(.inclk0(xclk),
|
||||
.c3(mclk),
|
||||
.locked(pll_locked)
|
||||
);
|
||||
|
||||
endmodule // thhor_crs
|
||||
|
|
@ -241,12 +241,12 @@ PEN XP/RSD-1 U2-8
|
|||
P_DOUT U5-3 U1-77
|
||||
nCSAp R4-4 U1-66
|
||||
nCSCp R2-4 U1-46
|
||||
OUTCp R2-2 U1-50
|
||||
DOUTCp R2-2 U1-50
|
||||
P106 P106-1 U1-106
|
||||
P111 P111-1 U1-111
|
||||
P105 P105-1 U1-105
|
||||
P_DIN U5-4 U1-80
|
||||
OUTAp R4-2 U1-68
|
||||
DOUTAp R4-2 U1-68
|
||||
DINCp R2-3 U1-49
|
||||
nCSDp R1-4 U1-39
|
||||
P33 P33-1 U1-33
|
||||
|
|
@ -255,12 +255,12 @@ P71 P71-1 U1-71
|
|||
SCKAp R4-1 U1-69
|
||||
DINAp R4-3 U1-67
|
||||
SCKBp R3-1 U1-65
|
||||
OUTBp R3-2 U1-60
|
||||
DOUTBp R3-2 U1-60
|
||||
DINBp R3-3 U1-59
|
||||
nCSBp R3-4 U1-58
|
||||
SCKCp R2-1 U1-51
|
||||
SCKDp R1-1 U1-44
|
||||
OUTDp R1-2 U1-43
|
||||
DOUTDp R1-2 U1-43
|
||||
DINDp R1-3 U1-42
|
||||
P144 P144-1 U1-144
|
||||
P143 P143-1 U1-143
|
||||
|
|
@ -279,8 +279,8 @@ P115 P115-1 U1-115
|
|||
P114 P114-1 U1-114
|
||||
P113 P113-1 U1-113
|
||||
P112 P112-1 U1-112
|
||||
D_OUT-F L41-5 U1-103
|
||||
D_OUT+F L41-6 U1-101
|
||||
D_OUT+F L41-5 U1-103
|
||||
D_OUT-F L41-6 U1-101
|
||||
CRCERR U2-3 U1-99
|
||||
S_IN+F R40-4 L40-5 U1-91
|
||||
S_IN-F R40-3 L40-6 U1-90
|
||||
|
|
@ -301,8 +301,8 @@ SCK U4-2 U2-13 U1-12 U1-11
|
|||
MISO U4-8 U2-12 U1-10
|
||||
nSTATUS U2-2 U1-9
|
||||
nCS U4-4 U2-9 U1-8
|
||||
P6 P6-1 U1-7
|
||||
P7 P7-1 U1-6
|
||||
P7 P7-1 U1-7
|
||||
P6 P6-1 U1-6
|
||||
Vpll C127-1 C126-1 C125-1 C124-1 C123-1 C122-1 C121-1 C120-1 C119-1 C118-1 C117-1 C116-1 C115-1 C114-1 C113-1 C112-1 C111-1 C110-1 U5-6 R74-2 XPLL/C3-1 XPLL/R1-1 XPLL/C2-2 XPLL/U1-5 U1-107 U1-35 U1-81 \
|
||||
U1-130 U1-117 U1-139 U1-122 U1-93 U1-75 U1-3
|
||||
GND C39-2 C38-2 C42-1 C37-1 C29-1 C28-1 C27-2 C26-2 C25-2 C20-2 C23-2 BOARD-1 C141-2 C140-2 CONN1-0 CONN1-32 CONN1-33 CONN1-34 CONN1-35 CONN1-36 CONN1-37 CONN1-20 CONN1-21 CONN1-22 CONN1-23 CONN1-24 \
|
||||
|
|
|
|||
|
|
@ -458,7 +458,7 @@ Symbol['T' 12.00mil]
|
|||
(
|
||||
SymbolLine[0.0000 10.00mil 30.00mil 10.00mil 8.00mil]
|
||||
SymbolLine[15.00mil 10.00mil 15.00mil 50.00mil 8.00mil]
|
||||
SymbolLine[0.0000 10.00mil 0.00mil 20.00mil 8.00mil]
|
||||
SymbolLine[0.0000 10.00mil 0.0000 20.00mil 8.00mil]
|
||||
SymbolLine[30.00mil 10.00mil 30.00mil 20.00mil 8.00mil]
|
||||
)
|
||||
Symbol['U' 12.00mil]
|
||||
|
|
@ -2417,7 +2417,7 @@ Element["" "C0603" "C101" "100nF" 16.8000mm 68.5000mm 0.0000 0.0000 3 55 ""]
|
|||
|
||||
)
|
||||
|
||||
Element["onsolder" "MSOP_3_8" "U3" "unknown" 18.9000mm 68.5000mm 0.0000 0.0000 2 50 "onsolder"]
|
||||
Element["onsolder" "MSOP_3_8" "U3" "ADM3061EBRM" 18.9000mm 68.5000mm 0.0000 0.0000 2 50 "onsolder"]
|
||||
(
|
||||
Pad[1.8000mm -0.9750mm 2.4000mm -0.9750mm 0.4000mm 20.00mil 0.5524mm "R" "1" "onsolder,square,edge2"]
|
||||
Pad[1.8000mm -0.3250mm 2.4000mm -0.3250mm 0.4000mm 20.00mil 0.5524mm "_RE_" "2" "onsolder,square,edge2"]
|
||||
|
|
@ -3531,14 +3531,14 @@ Element["" "PIN" "PG1" "unknown" 14.4000mm 67.3000mm 0.0000 0.0000 0 55 ""]
|
|||
|
||||
)
|
||||
|
||||
Element["" "PIN" "P7" "unknown" 15.8000mm 65.7000mm 0.0000 0.0000 0 55 ""]
|
||||
Element["" "PIN" "P6" "unknown" 15.8000mm 65.7000mm 0.0000 0.0000 0 55 ""]
|
||||
(
|
||||
Pin[0.0000 0.0000 0.7000mm 20.00mil 0.8524mm 0.3000mm "pin" "1" ""]
|
||||
ElementArc [0.0000 0.0000 0.5000mm 0.5000mm 180.000000 360.000000 0.1500mm]
|
||||
|
||||
)
|
||||
|
||||
Element["" "PIN" "P6" "unknown" 16.7000mm 65.7000mm 0.0000 0.0000 0 55 ""]
|
||||
Element["" "PIN" "P7" "unknown" 16.7000mm 65.7000mm 0.0000 0.0000 0 55 ""]
|
||||
(
|
||||
Pin[0.0000 0.0000 0.7000mm 20.00mil 0.8524mm 0.3000mm "pin" "1" ""]
|
||||
ElementArc [0.0000 0.0000 0.5000mm 0.5000mm 180.000000 360.000000 0.1500mm]
|
||||
|
|
@ -9912,7 +9912,7 @@ Layer(6 "bottom" "copper")
|
|||
[34.6257mm 34.4505mm] [34.7222mm 34.3071mm] [34.8648mm 34.2103mm] [35.0399mm 34.1746mm] [1386.40mil 34.2103mm]
|
||||
[1392.00mil 34.3071mm] [35.4527mm 34.4505mm] [35.4875mm 1363.20mil] [35.4727mm 34.7400mm] [35.4311mm 1371.80mil]
|
||||
[35.3662mm 34.9324mm] [35.2810mm 35.0030mm] [35.2589mm 35.0194mm] [35.2244mm 35.0402mm] [35.2163mm 35.0663mm]
|
||||
[35.2314mm 35.1037mm] [1387.60mil 35.1364mm] [35.4643mm 35.6656mm] [35.4781mm 35.6976mm] [1397.70mil 35.7540mm]
|
||||
[35.2314mm 35.1037mm] [35.2450mm 35.1364mm] [35.4643mm 35.6656mm] [35.4781mm 35.6976mm] [1397.70mil 35.7540mm]
|
||||
[35.5100mm 35.7638mm] [35.5235mm 35.7621mm] [35.5770mm 35.7348mm] [35.6089mm 35.7184mm] [35.6612mm 1405.10mil]
|
||||
[35.6913mm 35.6906mm] [1415.10mil 35.8627mm] [35.9726mm 35.8821mm] [1417.50mil 35.9040mm] [36.0321mm 35.9013mm]
|
||||
[1427.80mil 35.6670mm] [36.2923mm 35.6424mm] [36.3187mm 35.6148mm] [36.3212mm 35.5872mm] [1429.10mil 35.5555mm]
|
||||
|
|
@ -10678,8 +10678,8 @@ NetList()
|
|||
)
|
||||
Net("D_OUT+F" "(unknown)")
|
||||
(
|
||||
Connect("L41-6")
|
||||
Connect("U1-101")
|
||||
Connect("L41-5")
|
||||
Connect("U1-103")
|
||||
)
|
||||
Net("D_OUT-" "(unknown)")
|
||||
(
|
||||
|
|
@ -10688,8 +10688,8 @@ NetList()
|
|||
)
|
||||
Net("D_OUT-F" "(unknown)")
|
||||
(
|
||||
Connect("L41-5")
|
||||
Connect("U1-103")
|
||||
Connect("L41-6")
|
||||
Connect("U1-101")
|
||||
)
|
||||
Net("DINA" "(unknown)")
|
||||
(
|
||||
|
|
@ -10742,21 +10742,41 @@ NetList()
|
|||
Connect("A/U1-15")
|
||||
Connect("R4-7")
|
||||
)
|
||||
Net("DOUTAp" "(unknown)")
|
||||
(
|
||||
Connect("R4-2")
|
||||
Connect("U1-68")
|
||||
)
|
||||
Net("DOUTB" "(unknown)")
|
||||
(
|
||||
Connect("B/U1-15")
|
||||
Connect("R3-7")
|
||||
)
|
||||
Net("DOUTBp" "(unknown)")
|
||||
(
|
||||
Connect("R3-2")
|
||||
Connect("U1-60")
|
||||
)
|
||||
Net("DOUTC" "(unknown)")
|
||||
(
|
||||
Connect("C/U1-15")
|
||||
Connect("R2-7")
|
||||
)
|
||||
Net("DOUTCp" "(unknown)")
|
||||
(
|
||||
Connect("R2-2")
|
||||
Connect("U1-50")
|
||||
)
|
||||
Net("DOUTD" "(unknown)")
|
||||
(
|
||||
Connect("D/U1-15")
|
||||
Connect("R1-7")
|
||||
)
|
||||
Net("DOUTDp" "(unknown)")
|
||||
(
|
||||
Connect("R1-2")
|
||||
Connect("U1-43")
|
||||
)
|
||||
Net("GND" "(unknown)")
|
||||
(
|
||||
Connect("A/A/C4-2")
|
||||
|
|
@ -11306,35 +11326,15 @@ NetList()
|
|||
Connect("U1-9")
|
||||
Connect("U2-2")
|
||||
)
|
||||
Net("OUTAp" "(unknown)")
|
||||
(
|
||||
Connect("R4-2")
|
||||
Connect("U1-68")
|
||||
)
|
||||
Net("OUTBp" "(unknown)")
|
||||
(
|
||||
Connect("R3-2")
|
||||
Connect("U1-60")
|
||||
)
|
||||
Net("OUTCp" "(unknown)")
|
||||
(
|
||||
Connect("R2-2")
|
||||
Connect("U1-50")
|
||||
)
|
||||
Net("OUTDp" "(unknown)")
|
||||
(
|
||||
Connect("R1-2")
|
||||
Connect("U1-43")
|
||||
)
|
||||
Net("P6" "(unknown)")
|
||||
(
|
||||
Connect("P6-1")
|
||||
Connect("U1-7")
|
||||
Connect("U1-6")
|
||||
)
|
||||
Net("P7" "(unknown)")
|
||||
(
|
||||
Connect("P7-1")
|
||||
Connect("U1-6")
|
||||
Connect("U1-7")
|
||||
)
|
||||
Net("P28" "(unknown)")
|
||||
(
|
||||
|
|
|
|||
|
|
@ -1677,7 +1677,7 @@ netname=DINBp
|
|||
N 33000 39600 33000 40400 4
|
||||
{
|
||||
T 32975 40400 5 5 1 1 90 6 1
|
||||
netname=OUTBp
|
||||
netname=DOUTBp
|
||||
}
|
||||
N 34000 39600 34000 40400 4
|
||||
{
|
||||
|
|
@ -1697,7 +1697,7 @@ netname=DINAp
|
|||
N 34600 39600 34600 40400 4
|
||||
{
|
||||
T 34575 40400 5 5 1 1 90 6 1
|
||||
netname=OUTAp
|
||||
netname=DOUTAp
|
||||
}
|
||||
N 34800 39600 34800 40400 4
|
||||
{
|
||||
|
|
@ -1751,14 +1751,14 @@ N 36100 44300 40200 44300 4
|
|||
T 38300 44350 5 10 1 1 0 0 1
|
||||
netname=D_IN+F
|
||||
}
|
||||
N 36100 47100 40200 47100 4
|
||||
{
|
||||
T 38300 47150 5 10 1 1 0 0 1
|
||||
netname=D_OUT-F
|
||||
}
|
||||
N 36100 46700 40200 46700 4
|
||||
{
|
||||
T 38300 46750 5 10 1 1 0 0 1
|
||||
netname=D_OUT-F
|
||||
}
|
||||
N 36100 47100 40200 47100 4
|
||||
{
|
||||
T 38300 47150 5 10 1 1 0 0 1
|
||||
netname=D_OUT+F
|
||||
}
|
||||
N 36100 43900 37600 43900 4
|
||||
|
|
@ -4239,24 +4239,24 @@ T 27700 43400 5 5 0 1 0 6 1
|
|||
footprint=PAD
|
||||
}
|
||||
N 27300 43300 27700 43300 4
|
||||
C 27800 46600 1 0 1 PIN1.sym
|
||||
{
|
||||
T 27500 46900 5 10 1 1 0 4 1
|
||||
refdes=P6
|
||||
T 27500 46900 5 10 0 0 0 0 1
|
||||
net=P6:1
|
||||
T 27700 47000 5 5 0 1 0 6 1
|
||||
footprint=PIN
|
||||
}
|
||||
C 27800 46800 1 0 1 PIN1.sym
|
||||
{
|
||||
T 27500 47100 5 10 1 1 0 4 1
|
||||
refdes=P7
|
||||
refdes=P6
|
||||
T 27500 47100 5 10 0 0 0 0 1
|
||||
net=P7:1
|
||||
net=P6:1
|
||||
T 27700 47200 5 5 0 1 0 6 1
|
||||
footprint=PIN
|
||||
}
|
||||
C 27800 46600 1 0 1 PIN1.sym
|
||||
{
|
||||
T 27500 46900 5 10 1 1 0 4 1
|
||||
refdes=P7
|
||||
T 27500 46900 5 10 0 0 0 0 1
|
||||
net=P7:1
|
||||
T 27700 47000 5 5 0 1 0 6 1
|
||||
footprint=PIN
|
||||
}
|
||||
C 28100 48700 1 270 1 PIN1.sym
|
||||
{
|
||||
T 28400 49000 5 10 1 1 270 4 1
|
||||
|
|
@ -4549,12 +4549,12 @@ value=100Ω
|
|||
N 29600 39600 29600 40400 4
|
||||
{
|
||||
T 29575 40400 5 5 1 1 90 6 1
|
||||
netname=OUTDp
|
||||
netname=DOUTDp
|
||||
}
|
||||
N 31000 39600 31000 40400 4
|
||||
{
|
||||
T 30975 40400 5 5 1 1 90 6 1
|
||||
netname=OUTCp
|
||||
netname=DOUTCp
|
||||
}
|
||||
N 33200 39600 34000 39600 4
|
||||
C 47200 37400 1 0 1 DB37-1.sym
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue