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2 commits
c3dba4356d ... 7b36d564ed

Author SHA1 Message Date
Stephan I. Böttcher
7b36d564ed add U6: AND gate to drop DCLK while reading the bitfile from flash 2025-12-31 01:16:21 +01:00
Stephan I. Böttcher
cff46bc0fa remove old Vdio symbols 2025-12-31 00:43:47 +01:00
4 changed files with 165 additions and 63 deletions
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52
sym/and-gate.sym Normal file
View file

@ -0,0 +1,52 @@
v 20220529 2
L 300 200 300 800 3 0 0 0 -1 -1
T 700 900 5 10 0 0 0 0 1
device=74HC1G08
T 700 1100 5 10 0 0 0 0 1
slot=1
T 700 1300 5 10 0 0 0 0 1
numslots=3
T 700 1500 5 10 0 0 0 0 1
slotdef=1:1,2,4
T 700 1700 5 10 0 0 0 0 1
slotdef=2:1,3,4
A 300 500 300 270 180 3 0 0 0 -1 -1
P 600 500 800 500 1 0 1
{
T 700 550 5 8 1 1 0 0 1
pinnumber=4
T 700 450 5 8 0 1 0 2 1
pinseq=3
T 550 500 9 8 0 1 0 6 1
pinlabel=Y
T 550 500 5 8 0 1 0 8 1
pintype=out
}
P 300 700 100 700 1 0 1
{
T 200 750 5 8 1 1 0 6 1
pinnumber=1
T 200 650 5 8 0 1 0 8 1
pinseq=1
T 350 700 9 8 0 1 0 0 1
pinlabel=A
T 350 700 5 8 0 1 0 2 1
pintype=in
}
P 300 300 100 300 1 0 1
{
T 200 350 5 8 1 1 0 6 1
pinnumber=2
T 200 250 5 8 0 1 0 8 1
pinseq=2
T 350 300 9 8 0 1 0 0 1
pinlabel=B
T 350 300 5 8 0 1 0 2 1
pintype=in
}
T 450 500 8 10 1 1 0 4 1
refdes=U?
T 700 1900 5 10 0 0 0 0 1
footprint=SC70_5
T 700 2100 5 10 0 0 0 0 1
description=AND gates with 2 inputs

9
thhor_crs.net
View file

@ -232,8 +232,9 @@ B J1-4 U3-7
XAVR/byp XAVR/C2-1 XAVR/U1-3
XAVR/adj XAVR/R2-2 XAVR/R1-2 XAVR/U1-4
Vprim R68-2 XP/L1-2 L1-4 XAVR/C1-1 XAVR/U1-1
SCK U6-2 U4-2 U2-13
ISP J1-7 U2-10
Vtiny J1-5 C102-1 C101-1 C100-1 U4-5 U4-3 U4-6 U3-8 XAVR/C3-1 XAVR/R1-1 XAVR/C2-2 XAVR/U1-5 U2-1
Vtiny U6-5 J1-5 C102-1 C101-1 C100-1 U4-5 U4-3 U4-6 U3-8 XAVR/C3-1 XAVR/R1-1 XAVR/C2-2 XAVR/U1-5 U2-1
TxD U3-4 U2-7
RxD U3-1 U2-6
TxE U3-3 U2-5
@ -297,15 +298,15 @@ xclk U9-3 U1-22
Vio C138-1 C137-1 C136-1 C135-1 C134-1 C133-1 C132-1 C131-1 C130-1 U9-4 XIO/C3-1 XIO/R1-1 XIO/C2-2 XIO/U1-5 U1-62 U1-26 U1-56 U1-47 U1-40 U1-18 U1-17 U1-15
nCONFIG U2-4 U1-14
MOSI U4-1 U2-11 U1-13
SCK U4-2 U2-13 U1-12 U1-11
DCLK U6-4 U1-12 U1-11
MISO U4-8 U2-12 U1-10
nSTATUS U2-2 U1-9
nCS U4-4 U2-9 U1-8
nCS U6-1 U4-4 U2-9 U1-8
P7 P7-1 U1-7
P6 P6-1 U1-6
Vpll C127-1 C126-1 C125-1 C124-1 C123-1 C122-1 C121-1 C120-1 C119-1 C118-1 C117-1 C116-1 C115-1 C114-1 C113-1 C112-1 C111-1 C110-1 U5-6 R74-2 XPLL/C3-1 XPLL/R1-1 XPLL/C2-2 XPLL/U1-5 U1-107 U1-35 U1-81 \
U1-130 U1-117 U1-139 U1-122 U1-93 U1-75 U1-3
GND C39-2 C38-2 C42-1 C37-1 C29-1 C28-1 C27-2 C26-2 C25-2 C20-2 C23-2 BOARD-1 C141-2 C140-2 CONN1-0 CONN1-32 CONN1-33 CONN1-34 CONN1-35 CONN1-36 CONN1-37 CONN1-20 CONN1-21 CONN1-22 CONN1-23 CONN1-24 \
GND U6-3 C39-2 C38-2 C42-1 C37-1 C29-1 C28-1 C27-2 C26-2 C25-2 C20-2 C23-2 BOARD-1 C141-2 C140-2 CONN1-0 CONN1-32 CONN1-33 CONN1-34 CONN1-35 CONN1-36 CONN1-37 CONN1-20 CONN1-21 CONN1-22 CONN1-23 CONN1-24 \
CONN1-26 CONN1-27 CONN1-28 CONN1-29 CONN1-30 CONN1-31 PG2-1 PG1-1 C138-2 C127-2 C126-2 C137-2 C136-2 C125-2 C124-2 C123-2 C122-2 C171-2 C170-2 C169-2 C168-2 C151-2 C150-2 C167-2 C166-2 C165-2 C164-2 \
C163-2 C162-2 C161-2 C160-2 C159-2 C158-2 C157-2 C156-2 C155-2 C154-2 C153-2 C152-2 C135-2 C134-2 C133-2 C132-2 C131-2 C130-2 C121-2 C120-2 C119-2 C118-2 C117-2 C116-2 C115-2 C114-2 C113-2 C112-2 \
C111-2 C110-2 J1-8 J1-6 C102-2 C101-2 C100-2 C36-1 C35-2 C41-1 C40-1 U5-1 C63-1 R73-1 C62-1 R69-1 C60-1 C61-1 R67-1 C64-1 R61-1 C55-1 C54-1 C53-1 C52-1 C59-1 R64-1 C58-1 C57-1 R62-1 C56-1 U30-3 C34-1 \

94
thhor_crs.pcb
View file

@ -1166,6 +1166,7 @@ Via[30.7000mm 30.8000mm 1.0000mm 0.4000mm 0.8000mm 0.5000mm "" "thermal(3S)"]
Via[58.6000mm 50.6000mm 0.7000mm 0.4000mm 0.5000mm 0.3000mm "" ""]
Via[60.2000mm 14.6000mm 0.7000mm 0.4000mm 0.5000mm 0.3000mm "" "thermal(0S,3S)"]
Via[12.3000mm 10.4000mm 0.7000mm 0.4000mm 0.5000mm 0.3000mm "" ""]
Via[27.7000mm 65.0000mm 0.7000mm 0.4000mm 0.5000mm 0.3000mm "" ""]
Element["" "EIA7343" "C20" "220µF_16V" 35.4000mm 76.3000mm -0.6000mm -0.4000mm 0 55 ""]
(
@ -3566,28 +3567,28 @@ Element["" "PAD" "P23" "unknown" 25.6000mm 64.4000mm -0.2000mm -0.6000mm 0 22 ""
)
Element["" "PAD" "P28" "unknown" 28.1000mm 65.0000mm -0.3000mm -0.6000mm 0 22 ""]
Element["" "PAD" "P28" "unknown" 28.1000mm 64.2000mm -0.3000mm -0.6000mm 0 22 ""]
(
Pad[0.0000 0.0000 0.0000 0.0000 0.4000mm 0.3000mm 0.7000mm "pin" "1" ""]
ElementArc [0.0000 0.0000 0.2000mm 0.2000mm 180.000000 360.000000 0.0500mm]
)
Element["" "PAD" "P33" "unknown" 30.6000mm 64.5000mm -0.3000mm -0.6000mm 0 22 ""]
Element["" "PAD" "P33" "unknown" 30.6000mm 64.2000mm -0.3000mm -0.6000mm 0 22 ""]
(
Pad[0.0000 0.0000 0.0000 0.0000 0.4000mm 0.3000mm 0.7000mm "pin" "1" ""]
ElementArc [0.0000 0.0000 0.2000mm 0.2000mm 180.000000 360.000000 0.0500mm]
)
Element["" "PAD" "P32" "unknown" 30.1000mm 65.0000mm -0.3000mm -0.6000mm 0 22 ""]
Element["" "PAD" "P32" "unknown" 30.1000mm 64.6000mm -0.3000mm -0.6000mm 0 22 ""]
(
Pad[0.0000 0.0000 0.0000 0.0000 0.4000mm 0.3000mm 0.7000mm "pin" "1" ""]
ElementArc [0.0000 0.0000 0.2000mm 0.2000mm 180.000000 360.000000 0.0500mm]
)
Element["" "PAD" "P31" "unknown" 29.6000mm 64.5000mm -0.2000mm -0.6000mm 0 22 ""]
Element["" "PAD" "P31" "unknown" 29.6000mm 64.2000mm -0.2000mm -0.6000mm 0 22 ""]
(
Pad[0.0000 0.0000 0.0000 0.0000 0.4000mm 0.3000mm 0.7000mm "pin" "1" ""]
ElementArc [0.0000 0.0000 0.2000mm 0.2000mm 180.000000 360.000000 0.0500mm]
@ -7647,6 +7648,20 @@ Element["hidename" "C1206" "C27" "10µF_25V" 17.3000mm 13.1000mm -0.5000mm 0.600
ElementLine [-30.00mil 60.00mil 30.00mil 60.00mil 5.00mil]
ElementLine [30.00mil -60.00mil 30.00mil 60.00mil 5.00mil]
)
Element["" "SC70_5" "U6" "unknown" 30.0000mm 66.1000mm -0.4000mm 0.3500mm 1 50 ""]
(
Pad[0.6000mm 0.6500mm 39.37mil 0.6500mm 0.3000mm 20.00mil 0.4524mm "A" "1" "square,edge2"]
Pad[0.6000mm 0.0000 39.37mil 0.0000 0.3000mm 20.00mil 0.4524mm "B" "2" "square,edge2"]
Pad[0.6000mm -0.6500mm 39.37mil -0.6500mm 0.3000mm 20.00mil 0.4524mm "" "3" "square,edge2"]
Pad[-39.37mil -0.6500mm -0.6000mm -0.6500mm 0.3000mm 20.00mil 0.4524mm "Y" "4" "square"]
Pad[-39.37mil 0.6500mm -0.6000mm 0.6500mm 0.3000mm 20.00mil 0.4524mm "" "5" "square"]
ElementLine [0.6000mm -0.9750mm 0.6000mm 0.9750mm 5.00mil]
ElementLine [-0.6000mm -0.9750mm 0.6000mm -0.9750mm 5.00mil]
ElementLine [-0.6000mm -0.9750mm -0.6000mm 0.9750mm 5.00mil]
ElementLine [-0.6000mm 0.9750mm 0.6000mm 0.9750mm 5.00mil]
)
Layer(1 "top" "copper")
(
@ -7906,13 +7921,13 @@ Layer(1 "top" "copper")
Line[29.1000mm 62.3000mm 29.1000mm 62.7000mm 0.2000mm 0.4000mm "clearline"]
Line[28.6000mm 62.7000mm 28.6000mm 62.3000mm 0.2000mm 0.4000mm "clearline"]
Line[28.6000mm 62.3000mm 28.5000mm 61.8000mm 0.2000mm 0.4000mm "clearline"]
Line[30.6000mm 64.5000mm 30.6000mm 63.7000mm 0.2000mm 0.4000mm "clearline"]
Line[30.1000mm 63.7000mm 30.1000mm 65.0000mm 0.2000mm 0.4000mm "clearline"]
Line[29.6000mm 64.5000mm 29.6000mm 63.7000mm 0.2000mm 0.4000mm "clearline"]
Line[28.1000mm 65.0000mm 28.1000mm 63.7000mm 0.2000mm 0.4000mm "clearline"]
Line[30.6000mm 64.2000mm 30.6000mm 63.7000mm 0.2000mm 0.4000mm "clearline"]
Line[30.1000mm 63.7000mm 30.1000mm 64.6000mm 0.2000mm 0.4000mm "clearline"]
Line[29.6000mm 64.2000mm 29.6000mm 63.7000mm 0.2000mm 0.4000mm "clearline"]
Line[28.1000mm 64.2000mm 28.1000mm 63.7000mm 0.2000mm 0.4000mm "clearline"]
Line[25.6000mm 64.4000mm 25.6000mm 63.7000mm 0.2000mm 0.4000mm "clearline"]
Line[26.6000mm 63.7000mm 26.6000mm 64.4000mm 0.2000mm 0.4000mm "clearline"]
Line[26.6000mm 64.4000mm 27.6000mm 64.4000mm 0.2000mm 0.4000mm "clearline"]
Line[26.6000mm 64.4000mm 27.3000mm 64.4000mm 0.2000mm 0.4000mm "clearline"]
Line[26.1000mm 63.7000mm 26.1000mm 64.8000mm 0.2000mm 0.4000mm "clearline"]
Line[16.6000mm 62.8000mm 16.6000mm 62.3000mm 0.2000mm 0.4000mm "clearline"]
Line[16.1000mm 62.8000mm 16.1000mm 62.3000mm 0.2000mm 0.4000mm "clearline"]
@ -8060,7 +8075,7 @@ Layer(1 "top" "copper")
Line[12.3000mm 45.3000mm 11.4000mm 45.3000mm 0.2000mm 0.4000mm "clearline"]
Line[11.4000mm 45.3000mm 11.1000mm 45.2000mm 0.2000mm 0.4000mm "clearline"]
Line[11.1000mm 45.2000mm 10.6000mm 45.2000mm 0.2000mm 0.4000mm "clearline"]
Line[27.6000mm 63.7000mm 27.6000mm 64.4000mm 0.2000mm 0.4000mm "clearline"]
Line[27.6000mm 63.7000mm 27.6000mm 64.1000mm 0.2000mm 0.4000mm "clearline"]
Line[25.6000mm 64.4000mm 26.1000mm 64.8000mm 0.2000mm 0.4000mm "clearline"]
Line[26.1000mm 64.8000mm 26.6000mm 64.4000mm 0.2000mm 0.4000mm "clearline"]
Line[34.4000mm 58.3000mm 35.8000mm 58.3000mm 0.2000mm 0.4000mm "clearline"]
@ -8654,6 +8669,21 @@ Layer(1 "top" "copper")
Line[35.4000mm 35.9000mm 35.4000mm 34.2000mm 0.6000mm 0.4000mm "clearline"]
Line[30.7000mm 30.8000mm 30.7000mm 34.2000mm 0.6000mm 0.4000mm "clearline"]
Line[24.0000mm 30.7000mm 25.8000mm 30.7000mm 0.6000mm 0.4000mm "clearline"]
Line[27.6000mm 64.1000mm 27.3000mm 64.4000mm 0.2000mm 0.4000mm "clearline"]
Line[26.2000mm 68.9000mm 27.3000mm 68.9000mm 0.2000mm 0.4000mm "clearline"]
Line[27.3000mm 68.9000mm 28.5000mm 66.3000mm 0.2000mm 0.4000mm "clearline"]
Line[28.5000mm 66.3000mm 29.8000mm 66.3000mm 0.2000mm 0.4000mm "clearline"]
Line[29.8000mm 66.3000mm 30.3000mm 66.7500mm 0.2000mm 0.4000mm "clearline"]
Line[30.3000mm 66.7500mm 30.8000mm 66.7500mm 0.2000mm 0.4000mm "clearline"]
Line[32.1000mm 63.6000mm 32.1000mm 64.2000mm 0.2000mm 0.4000mm "clearline"]
Line[32.1000mm 64.2000mm 31.4000mm 65.4500mm 0.2000mm 0.4000mm "clearline"]
Line[31.4000mm 65.4500mm 30.8000mm 65.4500mm 0.2000mm 0.4000mm "clearline"]
Line[27.1000mm 65.9000mm 30.1000mm 65.9000mm 0.2000mm 0.4000mm "clearline"]
Line[30.1000mm 65.9000mm 30.4000mm 66.1000mm 0.2000mm 0.4000mm "clearline"]
Line[30.4000mm 66.1000mm 30.8000mm 66.1000mm 0.2000mm 0.4000mm "clearline"]
Line[29.1000mm 66.8000mm 29.1000mm 67.8000mm 0.2000mm 0.4000mm "clearline"]
Line[29.1000mm 65.4500mm 28.5000mm 65.4500mm 0.2000mm 0.4000mm "clearline"]
Line[28.5000mm 65.4500mm 27.7000mm 65.0000mm 0.2000mm 0.4000mm "clearline"]
Polygon("clearpoly")
(
[57.0000mm 14.0000mm] [61.0000mm 14.0000mm] [61.0000mm 17.5000mm] [57.0000mm 17.5000mm]
@ -8742,34 +8772,24 @@ Layer(5 "signal" "copper")
Line[43.2000mm 75.6000mm 41.8000mm 71.2000mm 0.2000mm 0.4000mm "clearline"]
Line[42.5000mm 75.9000mm 41.7000mm 72.4000mm 0.2000mm 0.4000mm "clearline"]
Line[41.7000mm 72.4000mm 39.0000mm 66.8000mm 0.2000mm 0.4000mm "clearline"]
Line[27.4000mm 66.8000mm 27.8000mm 66.2000mm 0.2000mm 0.4000mm "clearline"]
Line[27.1000mm 65.9000mm 25.0000mm 65.0000mm 0.2000mm 0.4000mm "clearline"]
Line[27.8000mm 66.2000mm 27.8000mm 65.6000mm 0.2000mm 0.4000mm "clearline"]
Line[23.0000mm 71.6000mm 18.2000mm 70.9000mm 0.2000mm 0.4000mm "clearline"]
Line[18.2000mm 70.9000mm 17.2000mm 70.9000mm 0.2000mm 0.4000mm "clearline"]
Line[14.9700mm 71.1900mm 17.2000mm 70.9000mm 0.2000mm 0.4000mm "clearline"]
Line[26.9000mm 67.6000mm 24.5000mm 66.3000mm 0.2000mm 0.4000mm "clearline"]
Line[24.5000mm 66.3000mm 21.0000mm 64.8000mm 0.2000mm 0.4000mm "clearline"]
Line[21.0000mm 67.7000mm 18.7000mm 67.6000mm 0.2000mm 0.4000mm "clearline"]
Line[26.9000mm 67.6000mm 25.8000mm 65.4000mm 0.2000mm 0.4000mm "clearline"]
Line[25.0000mm 64.8000mm 21.0000mm 64.8000mm 0.2000mm 0.4000mm "clearline"]
Line[21.8000mm 67.9000mm 18.7000mm 67.6000mm 0.2000mm 0.4000mm "clearline"]
Line[18.7000mm 67.6000mm 18.3000mm 67.2000mm 0.2000mm 0.4000mm "clearline"]
Line[18.3000mm 67.2000mm 18.1000mm 66.0000mm 0.2000mm 0.4000mm "clearline"]
Line[24.2000mm 66.9000mm 21.0000mm 67.7000mm 0.2000mm 0.4000mm "clearline"]
Line[24.2000mm 66.9000mm 21.8000mm 67.9000mm 0.2000mm 0.4000mm "clearline"]
Line[18.4000mm 64.5000mm 19.1000mm 66.9000mm 0.2000mm 0.4000mm "clearline"]
Line[18.4000mm 61.2000mm 18.4000mm 64.5000mm 0.2000mm 0.4000mm "clearline"]
Line[24.1000mm 44.2000mm 23.6000mm 43.8000mm 0.2000mm 0.4000mm "clearline"]
Line[24.1000mm 43.3000mm 23.4000mm 42.9000mm 0.2000mm 0.4000mm "clearline"]
Line[19.1000mm 44.8000mm 19.1000mm 60.2000mm 0.2000mm 0.4000mm "clearline"]
Line[21.5000mm 64.1000mm 20.7000mm 64.1000mm 0.2000mm 0.4000mm "clearline"]
Line[20.7000mm 64.1000mm 20.1000mm 64.9000mm 0.2000mm 0.4000mm "clearline"]
Line[27.8000mm 65.6000mm 27.5000mm 65.3000mm 0.2000mm 0.4000mm "clearline"]
Line[27.5000mm 65.3000mm 22.1000mm 63.7000mm 0.2000mm 0.4000mm "clearline"]
Line[22.1000mm 63.7000mm 20.0000mm 63.7000mm 0.2000mm 0.4000mm "clearline"]
Line[20.0000mm 63.7000mm 19.2500mm 64.6000mm 0.2000mm 0.4000mm "clearline"]
Line[23.6000mm 43.8000mm 18.7000mm 37.7000mm 0.2000mm 0.4000mm "clearline"]
Line[23.4000mm 42.9000mm 18.7000mm 37.0000mm 0.2000mm 0.4000mm "clearline"]
Line[18.7000mm 37.0000mm 18.1000mm 36.5000mm 0.2000mm 0.4000mm "clearline"]
Line[18.7000mm 37.7000mm 18.1000mm 37.4000mm 0.2000mm 0.4000mm "clearline"]
Line[25.0000mm 65.0000mm 21.5000mm 64.1000mm 0.2000mm 0.4000mm "clearline"]
Line[16.5000mm 39.7000mm 16.5000mm 32.7000mm 0.2000mm 0.4000mm "clearline"]
Line[16.5000mm 32.7000mm 17.1000mm 32.2000mm 0.2000mm 0.4000mm "clearline"]
Line[21.1000mm 31.5000mm 21.5000mm 30.9000mm 0.2000mm 0.4000mm "clearline"]
@ -9064,6 +9084,20 @@ Layer(5 "signal" "copper")
Line[52.6000mm 48.2000mm 58.6000mm 50.6000mm 0.6000mm 0.4000mm "clearline"]
Line[16.5500mm 20.4500mm 12.3000mm 11.3000mm 0.6000mm 0.4000mm "clearline"]
Line[12.3000mm 11.3000mm 12.3000mm 10.4000mm 0.6000mm 0.4000mm "clearline"]
Line[27.7000mm 65.0000mm 25.2000mm 64.1000mm 0.2000mm 0.4000mm "clearline"]
Line[25.2000mm 64.1000mm 20.6000mm 64.1000mm 0.2000mm 0.4000mm "clearline"]
Line[20.6000mm 64.1000mm 20.1000mm 64.9000mm 0.2000mm 0.4000mm "clearline"]
Line[25.8000mm 65.4000mm 25.0000mm 64.8000mm 0.2000mm 0.4000mm "clearline"]
Line[27.4000mm 66.8000mm 27.7000mm 67.4000mm 0.2000mm 0.4000mm "clearline"]
Line[27.7000mm 67.4000mm 27.7000mm 67.8000mm 0.2000mm 0.4000mm "clearline"]
Line[27.7000mm 67.8000mm 27.3000mm 68.4000mm 0.2000mm 0.4000mm "clearline"]
Line[27.3000mm 68.4000mm 26.4000mm 68.4000mm 0.2000mm 0.4000mm "clearline"]
Line[26.4000mm 68.4000mm 25.1000mm 66.6000mm 0.2000mm 0.4000mm "clearline"]
Line[25.1000mm 66.6000mm 24.1000mm 66.1000mm 0.2000mm 0.4000mm "clearline"]
Line[24.1000mm 66.1000mm 21.7000mm 67.4000mm 0.2000mm 0.4000mm "clearline"]
Line[21.7000mm 67.4000mm 21.1000mm 67.3000mm 0.2000mm 0.4000mm "clearline"]
Line[21.1000mm 67.3000mm 19.5000mm 65.3000mm 0.2000mm 0.4000mm "clearline"]
Line[19.5000mm 65.3000mm 19.2500mm 64.6000mm 0.2000mm 0.4000mm "clearline"]
)
Layer(6 "bottom" "copper")
(
@ -10692,6 +10726,12 @@ NetList()
Connect("L41-6")
Connect("U1-101")
)
Net("DCLK" "(unknown)")
(
Connect("U1-11")
Connect("U1-12")
Connect("U6-4")
)
Net("DINA" "(unknown)")
(
Connect("A/U1-14")
@ -11052,6 +11092,7 @@ NetList()
Connect("U3-5")
Connect("U4-7")
Connect("U5-1")
Connect("U6-3")
Connect("U9-1")
Connect("U9-2")
Connect("U30-3")
@ -11281,6 +11322,7 @@ NetList()
Connect("U1-8")
Connect("U2-9")
Connect("U4-4")
Connect("U6-1")
)
Net("nCSA" "(unknown)")
(
@ -11586,10 +11628,9 @@ NetList()
)
Net("SCK" "(unknown)")
(
Connect("U1-11")
Connect("U1-12")
Connect("U2-13")
Connect("U4-2")
Connect("U6-2")
)
Net("SCKA" "(unknown)")
(
@ -12030,6 +12071,7 @@ NetList()
Connect("U4-3")
Connect("U4-5")
Connect("U4-6")
Connect("U6-5")
Connect("XAVR/C2-2")
Connect("XAVR/C3-1")
Connect("XAVR/R1-1")

73
thhor_crs.sch
View file

@ -147,15 +147,6 @@ device=none
T 27200 45700 5 8 1 1 0 4 1
value=MOSI
}
C 27700 45800 1 0 1 io-1.sym
{
T 26800 46000 5 10 0 0 0 6 1
net=SCK:1
T 27500 46400 5 10 0 0 0 6 1
device=none
T 27200 45900 5 8 1 1 0 4 1
value=SCK
}
C 24900 44600 1 0 0 io-1.sym
{
T 25800 44800 5 10 0 0 0 0 1
@ -228,15 +219,6 @@ device=none
T 22200 45300 5 6 1 1 0 4 1
value=CRCERR
}
C 27700 46000 1 0 1 io-1.sym
{
T 26800 46200 5 10 0 0 0 6 1
net=SCK:1
T 27500 46600 5 10 0 0 0 6 1
device=none
T 27200 46100 5 8 1 1 0 4 1
value=SCK
}
C 27700 46200 1 0 1 io-1.sym
{
T 26800 46400 5 10 0 0 0 6 1
@ -4097,22 +4079,7 @@ net=GND:2
T 19350 47600 5 10 1 1 90 0 1
net=Vio:1
}
C 26600 45100 1 90 0 generic-power.sym
{
T 26300 45250 5 10 1 1 180 1 1
net=Vdio:1
}
C 27400 45200 1 270 0 gnd-1.sym
C 26600 44700 1 90 0 generic-power.sym
{
T 26300 44850 5 10 1 1 180 1 1
net=Vdio:1
}
C 26600 44500 1 90 0 generic-power.sym
{
T 26300 44650 5 10 1 1 180 1 1
net=Vdio:1
}
C 27600 44600 1 270 0 gnd-1.sym
C 27400 44200 1 270 0 gnd-1.sym
N 27900 44500 27700 44500 4
@ -5027,3 +4994,43 @@ net=VccP:1
}
T 36500 47500 9 8 1 0 0 1 1
not with LVDS
C 26300 45400 1 0 0 and-gate.sym
{
T 27000 46300 5 10 0 0 0 0 1
device=74HC1G08
T 26750 45900 5 10 1 1 0 4 1
refdes=U6
T 27000 47300 5 10 0 0 0 0 1
footprint=SC70_5
T 26300 45400 5 10 0 1 0 0 1
net=Vtiny:5
T 26300 45200 5 10 0 1 0 0 1
net=GND:3
}
N 27700 45900 27100 45900 4
{
T 27700 45950 5 5 1 1 0 6 1
netname=DCLK
}
N 27700 46100 27400 46100 4
N 27400 46100 27400 45900 4
C 26600 45600 1 0 1 io-1.sym
{
T 25700 45800 5 10 0 0 0 6 1
net=SCK:1
T 26400 46200 5 10 0 0 0 6 1
device=none
T 26100 45700 5 8 1 1 0 4 1
value=SCK
}
C 26600 46000 1 0 1 io-1.sym
{
T 25700 46200 5 10 0 0 0 6 1
net=nCS:1
T 26400 46600 5 10 0 0 0 6 1
device=none
T 26100 46100 5 8 1 1 0 4 1
value=nCS
}
N 26400 46100 26600 46100 4
N 26400 45700 26600 45700 4