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thhor_crs/sym
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Stephan I. Böttcher 7b36d564ed add U6: AND gate to drop DCLK while reading the bitfile from flash
2025-12-31 01:16:21 +01:00
..
10CL25E144.sym THHΘR Cosmic Ray Sensor 2025-12-16 19:11:12 +01:00
AD8005-1.sym sub schematics 2025-12-16 21:12:07 +01:00
ADC128S102-16.sym THHΘR Cosmic Ray Sensor 2025-12-16 19:11:12 +01:00
and-gate.sym add U6: AND gate to drop DCLK while reading the bitfile from flash 2025-12-31 01:16:21 +01:00
AT45DB081D-1.sym THHΘR Cosmic Ray Sensor 2025-12-16 19:11:12 +01:00
ATtiny404.sym THHΘR Cosmic Ray Sensor 2025-12-16 19:11:12 +01:00
CSA-1.sym THHΘR Cosmic Ray Sensor 2025-12-16 19:11:12 +01:00
dorn-adc.sym schematics mostly done 2025-12-16 22:58:21 +01:00
FSH-1.sym sub schematics 2025-12-16 21:12:07 +01:00
header8-2.sym FPGA placed, two sides connected 2025-12-18 03:52:01 +01:00
LDO-1.sym THHΘR Cosmic Ray Sensor 2025-12-16 19:11:12 +01:00
linefilter2-1.sym layout sepic and Vbias 2025-12-17 20:51:44 +01:00
linefilter4-1.sym layout sepic and Vbias 2025-12-17 20:51:44 +01:00
LT1761ES5-BYP.sym layout sepic and Vbias 2025-12-17 20:51:44 +01:00
LT1964ES5-BYP.sym layout sepic and Vbias 2025-12-17 20:51:44 +01:00
LT3580.sym layout sepic and Vbias 2025-12-17 20:51:44 +01:00
MS5534C.sym schematics mostly done 2025-12-16 22:58:21 +01:00
npn-sot23.sym sub schematics 2025-12-16 21:12:07 +01:00
PIN.sym schematics mostly done 2025-12-16 22:58:21 +01:00
PIN1.sym all FPGA blocking caps, unused pins 2025-12-19 01:01:32 +01:00
resistors-4.sym FPGA placed, two sides connected 2025-12-18 03:52:01 +01:00
rs485-hd8.sym layout sepic and Vbias 2025-12-17 20:51:44 +01:00
sepic.sym sub schematics 2025-12-16 21:12:07 +01:00
XO53.sym schematics mostly done 2025-12-16 22:58:21 +01:00