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ATtiny20.sym
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pcb: layout complete
|
2024-01-21 06:28:44 +01:00 |
|
ATtiny404.sym
|
pcb: layout complete
|
2024-01-21 06:28:44 +01:00 |
|
board.sym
|
pcb: layout complete
|
2024-01-21 06:28:44 +01:00 |
|
header2.sym
|
pcb: layout complete
|
2024-01-21 06:28:44 +01:00 |
|
header3.sym
|
CHIP rename, J1 w/ Vcc, BAT spec label, …
|
2024-01-22 20:23:12 +01:00 |
|
header4.sym
|
pcb: layout complete
|
2024-01-21 06:28:44 +01:00 |
|
LT1761ES5-SD.sym
|
pcb: layout complete
|
2024-01-21 06:28:44 +01:00 |
|
MS5534C.sym
|
pcb: layout complete
|
2024-01-21 06:28:44 +01:00 |