quartus/spwirena.fit.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
quartus/spwirena.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
quartus/spwirena.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
quartus/spwirena.fit.rpt:Warning (176674): Following 7 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
quartus/spwirena.fit.rpt: Warning (176118): Pin "T2xData" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "T2xData(n)"
quartus/spwirena.fit.rpt: Warning (176118): Pin "T2xStrobe" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "T2xStrobe(n)"
quartus/spwirena.fit.rpt: Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
quartus/spwirena.fit.rpt: Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
quartus/spwirena.fit.rpt: Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
quartus/spwirena.fit.rpt: Warning (176118): Pin "R2xData" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "R2xData(n)"
quartus/spwirena.fit.rpt: Warning (176118): Pin "R2xStrobe" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "R2xStrobe(n)"
quartus/spwirena.fit.rpt:Warning (169177): 21 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
quartus/spwirena.fit.rpt:Warning (169064): Following 17 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
quartus/spwirena.map.rpt:; errsum ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwirena.map.rpt:; almost_full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwirena.map.rpt:; fifo_hval ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwirena.map.rpt:; tc_fifo_hval ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwirena.map.rpt:; tick ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwirena.map.rpt:; errsum ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwirena.map.rpt:; almost_full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwirena.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwirena.map.rpt:; attn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
quartus/spwirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at spwirena_core.v(88): Parameter Declaration in module "spwirena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(150): truncated value with size 32 to match size of target (10)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(171): truncated value with size 32 to match size of target (10)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(111): truncated value with size 32 to match size of target (15)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(127): truncated value with size 32 to match size of target (9)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(132): truncated value with size 32 to match size of target (9)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(147): truncated value with size 32 to match size of target (10)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(165): truncated value with size 32 to match size of target (16)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(315): truncated value with size 32 to match size of target (8)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(43): truncated value with size 32 to match size of target (16)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(44): truncated value with size 32 to match size of target (16)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(111): truncated value with size 32 to match size of target (15)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(127): truncated value with size 32 to match size of target (9)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(132): truncated value with size 32 to match size of target (9)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(147): truncated value with size 32 to match size of target (10)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(165): truncated value with size 32 to match size of target (16)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(315): truncated value with size 32 to match size of target (8)
quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena.v(350): truncated value with size 32 to match size of target (7)
quartus/spwirena.map.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
quartus/spwirena.map.rpt:Warning (21074): Design contains 1 input pin(s) that do not drive logic
