dba49942ad
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@7134 bc5caf13-1734-44f8-af43-603852e9ee25
117 lines
16 KiB
Text
117 lines
16 KiB
Text
quartus/spwirena.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
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quartus/spwirena.fit.rpt: 5. I/O Assignment Warnings
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quartus/spwirena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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quartus/spwirena.fit.rpt:; I/O Assignment Warnings ;
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quartus/spwirena.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
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quartus/spwirena.fit.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
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quartus/spwirena.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
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quartus/spwirena.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
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quartus/spwirena.fit.rpt:Warning (176674): Following 7 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
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quartus/spwirena.fit.rpt: Warning (176118): Pin "T2xData" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "T2xData(n)"
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quartus/spwirena.fit.rpt: Warning (176118): Pin "T2xStrobe" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "T2xStrobe(n)"
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quartus/spwirena.fit.rpt: Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
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quartus/spwirena.fit.rpt: Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
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quartus/spwirena.fit.rpt: Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
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quartus/spwirena.fit.rpt: Warning (176118): Pin "R2xData" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "R2xData(n)"
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quartus/spwirena.fit.rpt: Warning (176118): Pin "R2xStrobe" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "R2xStrobe(n)"
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quartus/spwirena.fit.rpt:Warning (169177): 21 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
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quartus/spwirena.fit.rpt:Warning (169064): Following 17 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
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quartus/spwirena.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 14 warnings
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quartus/spwirena.map.rpt:; errsum ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/spwirena.map.rpt:; almost_full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/spwirena.map.rpt:; fifo_hval ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/spwirena.map.rpt:; tc_fifo_hval ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/spwirena.map.rpt:; tick ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/spwirena.map.rpt:; errsum ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/spwirena.map.rpt:; almost_full ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/spwirena.map.rpt:; halffull ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/spwirena.map.rpt:; attn ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ;
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quartus/spwirena.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
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quartus/spwirena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/serializer.v(188)
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quartus/spwirena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at spwirena_core.v(88): Parameter Declaration in module "spwirena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(254): truncated value with size 32 to match size of target (8)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(150): truncated value with size 32 to match size of target (10)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(171): truncated value with size 32 to match size of target (10)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(111): truncated value with size 32 to match size of target (15)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(127): truncated value with size 32 to match size of target (9)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(132): truncated value with size 32 to match size of target (9)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(147): truncated value with size 32 to match size of target (10)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(165): truncated value with size 32 to match size of target (16)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(315): truncated value with size 32 to match size of target (8)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(509): truncated value with size 32 to match size of target (8)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(526): truncated value with size 32 to match size of target (8)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(527): truncated value with size 32 to match size of target (4)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(584): truncated value with size 32 to match size of target (12)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(593): truncated value with size 32 to match size of target (12)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(595): truncated value with size 32 to match size of target (3)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(606): truncated value with size 32 to match size of target (12)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(622): truncated value with size 32 to match size of target (12)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(246): truncated value with size 4 to match size of target (3)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(248): truncated value with size 32 to match size of target (3)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(296): truncated value with size 32 to match size of target (4)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at SpW.v(397): truncated value with size 32 to match size of target (8)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(43): truncated value with size 32 to match size of target (16)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(44): truncated value with size 32 to match size of target (16)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(111): truncated value with size 32 to match size of target (15)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(127): truncated value with size 32 to match size of target (9)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(132): truncated value with size 32 to match size of target (9)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(147): truncated value with size 32 to match size of target (10)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(165): truncated value with size 32 to match size of target (16)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena_core.v(315): truncated value with size 32 to match size of target (8)
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quartus/spwirena.map.rpt:Warning (10230): Verilog HDL assignment warning at spwirena.v(350): truncated value with size 32 to match size of target (7)
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quartus/spwirena.map.rpt:Warning (14284): Synthesized away the following node(s):
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quartus/spwirena.map.rpt: Warning (14285): Synthesized away the following RAM node(s):
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quartus/spwirena.map.rpt: Warning (14320): Synthesized away node "spwirena_core:core2|spififo:tx_fifo|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[8]"
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quartus/spwirena.map.rpt: Warning (14320): Synthesized away node "spwirena_core:core2|spififo:tx_fifo|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[9]"
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quartus/spwirena.map.rpt: Warning (14320): Synthesized away node "spwirena_core:core2|spififo:tx_fifo|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[10]"
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quartus/spwirena.map.rpt: Warning (14320): Synthesized away node "spwirena_core:core2|spififo:tx_fifo|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[11]"
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quartus/spwirena.map.rpt: Warning (14320): Synthesized away node "spwirena_core:core2|spififo:tx_fifo|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[12]"
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quartus/spwirena.map.rpt: Warning (14320): Synthesized away node "spwirena_core:core|spififo:tx_fifo|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[8]"
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quartus/spwirena.map.rpt: Warning (14320): Synthesized away node "spwirena_core:core|spififo:tx_fifo|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[9]"
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quartus/spwirena.map.rpt: Warning (14320): Synthesized away node "spwirena_core:core|spififo:tx_fifo|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[10]"
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quartus/spwirena.map.rpt: Warning (14320): Synthesized away node "spwirena_core:core|spififo:tx_fifo|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[11]"
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quartus/spwirena.map.rpt: Warning (14320): Synthesized away node "spwirena_core:core|spififo:tx_fifo|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[12]"
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quartus/spwirena.map.rpt:Warning (12241): 7 hierarchies have connectivity warnings - see the Connectivity Checks report folder
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quartus/spwirena.map.rpt:Warning (13034): The following nodes have both tri-state and non-tri-state drivers
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quartus/spwirena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "LEFT[9]" and its non-tri-state driver.
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quartus/spwirena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "LEFT[8]" and its non-tri-state driver.
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quartus/spwirena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "LEFT[5]" and its non-tri-state driver.
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quartus/spwirena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "LEFT[4]" and its non-tri-state driver.
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quartus/spwirena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "LEFT[3]" and its non-tri-state driver.
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quartus/spwirena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "LEFT[2]" and its non-tri-state driver.
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quartus/spwirena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "LEFT[1]" and its non-tri-state driver.
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quartus/spwirena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "LEFT[0]" and its non-tri-state driver.
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quartus/spwirena.map.rpt:Warning (13039): The following bidir pins have no drivers
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quartus/spwirena.map.rpt: Warning (13040): Bidir "LEFT[16]" has no driver
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quartus/spwirena.map.rpt: Warning (13040): Bidir "LEFT[15]" has no driver
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quartus/spwirena.map.rpt: Warning (13040): Bidir "LEFT[14]" has no driver
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quartus/spwirena.map.rpt: Warning (13040): Bidir "LEFT[13]" has no driver
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quartus/spwirena.map.rpt: Warning (13040): Bidir "LEFT[12]" has no driver
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quartus/spwirena.map.rpt: Warning (13040): Bidir "LEFT[11]" has no driver
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quartus/spwirena.map.rpt: Warning (13040): Bidir "LEFT[10]" has no driver
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quartus/spwirena.map.rpt: Warning (13040): Bidir "LEFT[7]" has no driver
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quartus/spwirena.map.rpt: Warning (13040): Bidir "LEFT[6]" has no driver
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quartus/spwirena.map.rpt:Warning (13009): TRI or OPNDRN buffers permanently enabled
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quartus/spwirena.map.rpt: Warning (13010): Node "LEFT[9]~synth"
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quartus/spwirena.map.rpt: Warning (13010): Node "LEFT[8]~synth"
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quartus/spwirena.map.rpt: Warning (13010): Node "LEFT[5]~synth"
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quartus/spwirena.map.rpt: Warning (13010): Node "LEFT[4]~synth"
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quartus/spwirena.map.rpt: Warning (13010): Node "LEFT[3]~synth"
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quartus/spwirena.map.rpt: Warning (13010): Node "LEFT[2]~synth"
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quartus/spwirena.map.rpt: Warning (13010): Node "LEFT[1]~synth"
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quartus/spwirena.map.rpt: Warning (13010): Node "LEFT[0]~synth"
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quartus/spwirena.map.rpt:Warning (15901): PLL "pll384:pll0|altpll:altpll_component|altpll_r273:auto_generated|pll1" has parameter clk0_counter set to C0 specified but port CLK[0] is not connected
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quartus/spwirena.map.rpt:Warning (21074): Design contains 1 input pin(s) that do not drive logic
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quartus/spwirena.map.rpt: Warning (15610): No output dependent on input pin "RxStrobe[2]"
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quartus/spwirena.map.rpt:Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 83 warnings
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quartus/spwirena.sta.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
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quartus/spwirena.sta.rpt:Critical Warning (332148): Timing requirements not met
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quartus/spwirena.sta.rpt:Critical Warning (332148): Timing requirements not met
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quartus/spwirena.sta.rpt:Critical Warning (332148): Timing requirements not met
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quartus/spwirena.sta.rpt:Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
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