2013-05-17 14:53:15 +00:00
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How to work with the Libero IDE on existing projects (by Martin, 17. May 2013)
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The version of the Libero IDE this tutorial is based upon is 9.1.5.1 SP5.
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In order to better handle constraints files, the Synplify Pro software has been
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updated to version G-2012.09A-SP1, which can be obtained somwhere on
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Actels webpage.
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1) Open the *.prj-file with Libero IDE. Several error messages will appear due to
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missing files (which you will create automatically in the following steps). Do not bother.
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2A) Click on "Synthesis" in the project flow tab.
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2B) Import synthesis constraint file by Implementation Options -> Constraints -> <click to add file...>
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and open "syn_const.sdc" (or any other constraints file). Unfortunately, Synplify Pro forgets
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about this step after closure, so you have to repeat this every time you re-open Synplify
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2013-08-01 10:41:24 +00:00
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(IMPORTANT! Disable FSM Compiler)
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2013-05-17 14:53:15 +00:00
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2C) Hit F8 or Run->Run. Let the tool finish.
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3A) Open Designer by clicking on "Place & Route" in the project flow tab.
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Add the physical design constraints file and confirm. Choose the appropriate values from
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the following dialouge boxes:
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RTAX2000S, 256 CQFP, Speed STD -> IO-Standards as desired -> Operating Conditions as desired
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3B) Import the pinout file if desired by File -> Import Source Files... -> Add -> ...
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Confirm the following dialouges with default values
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3C) Click on "Compile" and choose default options in the following dialouges (or adjust if
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necessary). Wait for tool to finish.
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Check, if your clock-signals are connected to the hardwired clock network by scrolling
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a little up through the produced log in the bottom og the screen. There should be
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something like this:
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Post-Combiner device utilization:
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SEQUENTIAL (R-cells) Used: 6671 Total: 10752 (62.04%)
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COMB (C-cells) Used: 10618 Total: 21504 (49.38%)
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LOGIC (R+C cells) Used: 17289 Total: 32256 (53.60%)
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RAM/FIFO Used: 23 Total: 64
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IO w/Clocks Used: 56 Total: 136
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CLOCK (Routed) Used: 0 Total: 4
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HCLOCK (Hardwired) Used: 1 Total: 4
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PLL Used: 0 Total: 0
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Do the same for your other global signals, which should be either mapped to hardwired
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(HCLOCK) or routed (CLOCK) nets.
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3D) Click on "Layout". Leave settings in the following dialouge at their defaults or
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adjust as you see fit. Let the tool finish.
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3E) Click on "Generate Programming File..." and do the necessary adjustments in
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the following dialouge box.
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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!!! IMPORTANT: For flight hardware, the option "Use the JTAG pull-up resistor" !!!
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!!! has to be DISABLED. Otherwise we might lose the entire Chip to !!!
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!!! an SEU (you do not want that, do you??) !!!
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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Let the tool finish.
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