34c3a1c86e
git-svn-id: svn+ssh://asterix.ieap.uni-kiel.de/home/subversion/stephan/solo/eda@8054 bc5caf13-1734-44f8-af43-603852e9ee25
189 lines
28 KiB
Text
189 lines
28 KiB
Text
quartus/darena.asm.rpt:Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
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quartus/darena.fit.rpt: 5. I/O Assignment Warnings
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quartus/darena.fit.rpt:; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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quartus/darena.fit.rpt:; I/O Assignment Warnings ;
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quartus/darena.fit.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
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quartus/darena.fit.rpt:Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
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quartus/darena.fit.rpt:Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
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quartus/darena.fit.rpt:Warning (176674): Following 7 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins.
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quartus/darena.fit.rpt: Warning (176118): Pin "clk_T1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_T1(n)"
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quartus/darena.fit.rpt: Warning (176118): Pin "spi_miso" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_miso(n)"
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quartus/darena.fit.rpt: Warning (176118): Pin "trigger" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "trigger(n)"
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quartus/darena.fit.rpt: Warning (176118): Pin "adc_clk" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "adc_clk(n)"
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quartus/darena.fit.rpt: Warning (176118): Pin "spi_sck" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_sck(n)"
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quartus/darena.fit.rpt: Warning (176118): Pin "clk_12" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "clk_12(n)"
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quartus/darena.fit.rpt: Warning (176118): Pin "spi_mosi" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "spi_mosi(n)"
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quartus/darena.fit.rpt:Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
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quartus/darena.fit.rpt:Warning (176251): Ignoring some wildcard destinations of fast I/O register assignments
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quartus/darena.fit.rpt:Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
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quartus/darena.fit.rpt:Warning (169064): Following 14 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
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quartus/darena.fit.rpt:Info: Quartus II 32-bit Fitter was successful. 0 errors, 15 warnings
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quartus/darena.map.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
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quartus/darena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(13)
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quartus/darena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(15)
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quartus/darena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(63)
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quartus/darena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(106)
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quartus/darena.map.rpt:Warning (10335): Unrecognized synthesis attribute "synthesis" at ../../altera/adc128s102.v(120)
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(54): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(55): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(57): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(58): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(59): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(60): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(61): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(62): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(64): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(55): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(56): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(57): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(58): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(59): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(61): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(62): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(64): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(65): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(66): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(67): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(69): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(70): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(72): Parameter Declaration in module "dorn_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(215): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(216): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(217): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(218): Parameter Declaration in module "dorn_l1" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(467): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(468): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(469): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(470): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(471): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(472): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(473): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(474): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(475): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(476): Parameter Declaration in module "dorn_l2" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(732): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(733): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at dorn.v(734): Parameter Declaration in module "dorn_l3" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at divider.v(20): Parameter Declaration in module "dorn_divide" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(146): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(147): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10222): Verilog HDL Parameter Declaration warning at darena.v(148): Parameter Declaration in module "darena_core" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
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quartus/darena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at arena.v(382): object "tick_reset" assigned a value but never read
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(97): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(99): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(256): truncated value with size 32 to match size of target (8)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_slave.v(258): truncated value with size 32 to match size of target (8)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(70): truncated value with size 32 to match size of target (3)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(150): truncated value with size 32 to match size of target (10)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at packetfifo.v(171): truncated value with size 32 to match size of target (10)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (5)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at countbits.v(13): truncated value with size 32 to match size of target (10)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at darena.v(160): truncated value with size 32 to match size of target (16)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at darena.v(220): truncated value with size 32 to match size of target (16)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at darena.v(237): truncated value with size 32 to match size of target (12)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at darena.v(257): truncated value with size 32 to match size of target (11)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at scangen.v(64): truncated value with size 5 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at scangen.v(91): truncated value with size 32 to match size of target (2)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(125): truncated value with size 32 to match size of target (8)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(143): truncated value with size 32 to match size of target (8)
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quartus/darena.map.rpt:Warning (10036): Verilog HDL or VHDL warning at dorn.v(238): object "adc_valid" assigned a value but never read
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(265): truncated value with size 32 to match size of target (3)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(270): truncated value with size 4 to match size of target (3)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(297): truncated value with size 32 to match size of target (5)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(303): truncated value with size 32 to match size of target (3)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(310): truncated value with size 9 to match size of target (8)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(315): truncated value with size 10 to match size of target (9)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(327): truncated value with size 32 to match size of target (3)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(343): truncated value with size 32 to match size of target (8)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(368): truncated value with size 13 to match size of target (12)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(418): truncated value with size 32 to match size of target (13)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(75): truncated value with size 32 to match size of target (2)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc128s102.v(163): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(531): truncated value with size 32 to match size of target (13)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(540): truncated value with size 32 to match size of target (3)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(547): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(569): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(573): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(598): truncated value with size 32 to match size of target (2)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(600): truncated value with size 32 to match size of target (2)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(612): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(614): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(631): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(641): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(642): truncated value with size 32 to match size of target (3)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(669): truncated value with size 32 to match size of target (26)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(685): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(777): truncated value with size 32 to match size of target (2)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dorn.v(791): truncated value with size 32 to match size of target (2)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(31): truncated value with size 26 to match size of target (25)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(32): truncated value with size 26 to match size of target (25)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(33): truncated value with size 32 to match size of target (15)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(48): truncated value with size 26 to match size of target (25)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(50): truncated value with size 26 to match size of target (25)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(74): truncated value with size 32 to match size of target (15)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(76): truncated value with size 16 to match size of target (15)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(77): truncated value with size 32 to match size of target (6)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at divider.v(82): truncated value with size 32 to match size of target (6)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at spi_master_adc.v(99): truncated value with size 32 to match size of target (4)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at adc_data.v(25): truncated value with size 32 to match size of target (2)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at oscilloscope.v(78): truncated value with size 32 to match size of target (12)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at oscilloscope.v(140): truncated value with size 32 to match size of target (16)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dornpulse.v(26): truncated value with size 32 to match size of target (3)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dornpulse.v(38): truncated value with size 32 to match size of target (3)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dornpulse.v(40): truncated value with size 32 to match size of target (3)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dornpulse.v(44): truncated value with size 32 to match size of target (6)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at dornpulse.v(77): truncated value with size 32 to match size of target (12)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at ltc2656.v(41): truncated value with size 32 to match size of target (10)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at ltc2656.v(43): truncated value with size 32 to match size of target (10)
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quartus/darena.map.rpt:Warning (10230): Verilog HDL assignment warning at ltc2656.v(45): truncated value with size 32 to match size of target (10)
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quartus/darena.map.rpt:Warning (14284): Synthesized away the following node(s):
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quartus/darena.map.rpt: Warning (14285): Synthesized away the following RAM node(s):
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quartus/darena.map.rpt: Warning (14320): Synthesized away node "darena_core:core|oscilloscope:scope|spififo:buffer|scfifo:scfifo_component|scfifo_p0c1:auto_generated|a_dpfifo_0g81:dpfifo|altsyncram_l2g1:FIFOram|q_b[15]"
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quartus/darena.map.rpt:Warning (13034): The following nodes have both tri-state and non-tri-state drivers
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quartus/darena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[5]" and its non-tri-state driver.
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quartus/darena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[6]" and its non-tri-state driver.
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quartus/darena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[7]" and its non-tri-state driver.
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quartus/darena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[8]" and its non-tri-state driver.
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quartus/darena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[10]" and its non-tri-state driver.
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quartus/darena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[11]" and its non-tri-state driver.
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quartus/darena.map.rpt: Warning (13035): Inserted always-enabled tri-state buffer between "AC[12]" and its non-tri-state driver.
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quartus/darena.map.rpt:Warning (13039): The following bidir pins have no drivers
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quartus/darena.map.rpt: Warning (13040): Bidir "AC[1]" has no driver
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quartus/darena.map.rpt: Warning (13040): Bidir "adc_mode" has no driver
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quartus/darena.map.rpt:Warning (13032): The following tri-state nodes are fed by constants
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quartus/darena.map.rpt: Warning (13033): The pin "AC[0]" is fed by GND
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quartus/darena.map.rpt: Warning (13033): The pin "AC[2]" is fed by GND
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quartus/darena.map.rpt: Warning (13033): The pin "AC[3]" is fed by GND
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quartus/darena.map.rpt: Warning (13033): The pin "AC[4]" is fed by GND
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quartus/darena.map.rpt: Warning (13033): The pin "AC[9]" is fed by GND
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quartus/darena.map.rpt:Warning (13009): TRI or OPNDRN buffers permanently enabled
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quartus/darena.map.rpt: Warning (13010): Node "AC[5]~synth"
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quartus/darena.map.rpt: Warning (13010): Node "AC[6]~synth"
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quartus/darena.map.rpt: Warning (13010): Node "AC[7]~synth"
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quartus/darena.map.rpt: Warning (13010): Node "AC[8]~synth"
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quartus/darena.map.rpt: Warning (13010): Node "AC[10]~synth"
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quartus/darena.map.rpt: Warning (13010): Node "AC[11]~synth"
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quartus/darena.map.rpt: Warning (13010): Node "AC[12]~synth"
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quartus/darena.map.rpt:Warning (13024): Output pins are stuck at VCC or GND
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quartus/darena.map.rpt: Warning (13410): Pin "ATxp[2]" is stuck at GND
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quartus/darena.map.rpt: Warning (13410): Pin "ATxp[1]" is stuck at GND
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quartus/darena.map.rpt: Warning (13410): Pin "debug[6]" is stuck at GND
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quartus/darena.map.rpt: Warning (13410): Pin "debug[5]" is stuck at GND
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quartus/darena.map.rpt: Warning (13410): Pin "debug[4]" is stuck at GND
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quartus/darena.map.rpt: Warning (13410): Pin "debug[3]" is stuck at GND
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quartus/darena.map.rpt: Warning (13410): Pin "debug[1]" is stuck at GND
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quartus/darena.map.rpt:Warning (15899): PLL "pll96:pll0|altpll:altpll_component|altpll_lm43:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
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quartus/darena.map.rpt:Warning (21074): Design contains 10 input pin(s) that do not drive logic
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quartus/darena.map.rpt: Warning (15610): No output dependent on input pin "clk_T1"
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quartus/darena.map.rpt: Warning (15610): No output dependent on input pin "trigger"
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quartus/darena.map.rpt: Warning (15610): No output dependent on input pin "Rx[4]"
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quartus/darena.map.rpt: Warning (15610): No output dependent on input pin "Rx[3]"
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quartus/darena.map.rpt: Warning (15610): No output dependent on input pin "ARx[6]"
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quartus/darena.map.rpt: Warning (15610): No output dependent on input pin "ARx[5]"
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quartus/darena.map.rpt: Warning (15610): No output dependent on input pin "ARx[4]"
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quartus/darena.map.rpt: Warning (15610): No output dependent on input pin "ARx[3]"
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quartus/darena.map.rpt: Warning (15610): No output dependent on input pin "ARx[2]"
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quartus/darena.map.rpt: Warning (15610): No output dependent on input pin "ARx[1]"
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quartus/darena.map.rpt:Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 166 warnings
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quartus/darena.sta.rpt:Warning (20028): Parallel compilation is not licensed and has been disabled
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quartus/darena.sta.rpt:Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning
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