353 lines
11 KiB
Verilog
353 lines
11 KiB
Verilog
//
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// ALTERA megafunctions for plls and simulation models
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`ifdef SIMULATION
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`timescale 1ns/1ps
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module pll192
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(
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input inclk0, // 12 MHz
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output reg c0, // 192 MHz
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output reg c1, // 96 MHz
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output reg c2, // 64 MHz
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output reg c3, // 32 MHz
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output reg c4, // 16 MHz
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output reg locked
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);
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always @(posedge inclk0)
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begin
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#0 c0 = 1;
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#2.604 c0 = 0; // 1/192MHz = 5.208ns -> 2.604ns
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repeat (15) // still 19 or 16?
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// 20*4.167(old value) = 83.34ns -> 83.34/5.208 = 16
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begin
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#2.604 c0 = 1;
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#2.604 c0 = 0;
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end
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end
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always @(posedge inclk0)
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begin
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#2.604 c1 = 1;
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#5.208 c1 = 0; // 1/96MHz = 10.417 -> 5.208ns
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repeat (7) //still 39?
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begin
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#5.208 c1 = 1;
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#5.208 c1 = 0;
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end
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locked <= 1;
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end
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always @(posedge inclk0)
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begin
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#0 c2 = 1;
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#7.8125 c2 = 0; // 1/64MHz = 15.625 -> 7.8125ns
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repeat (15)
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begin
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#7.8215 c2 = 1;
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#7.8215 c2 = 0;
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end
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end
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always @(posedge inclk0)
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begin
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#7.8125 c3 = 1;
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#15.625 c3 = 0; // 1/32MHz = 31.25 -> 15.625ns
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repeat (7)
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begin
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#15.625 c3 = 1;
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#15.625 c3 = 0;
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end
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end
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always @(posedge inclk0)
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begin
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#15.625 c4 = 1;
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#31.25 c4 = 0; // 1/16MHz = 62.5 -> 31.25ns
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repeat (3)
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begin
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#31.25 c4 = 1;
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#31.25 c4 = 0;
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end
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end
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endmodule // pll192
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`else
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`ifndef PLL_LOW_LEVEL
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module pll192
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(
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input inclk0,
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output c0, c1, c2, c3, c4,
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output locked
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);
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// inclk 12 MHz
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//
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// "192.000000"
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// "96.000000"
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// "64.000000"
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// "32.000000"
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// "16.000000"
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altpll altpll_component
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(
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.inclk ({1'b0, inclk0}),
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.clk ({c4, c3, c2, c1, c0}),
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.locked (locked),
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.activeclock (),
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.areset (1'b0),
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.clkbad (),
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.clkena ({6{1'b1}}),
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.clkloss (),
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.clkswitch (1'b0),
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.configupdate (1'b0),
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.enable0 (),
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.enable1 (),
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.extclk (),
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.extclkena ({4{1'b1}}),
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.fbin (1'b1),
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.fbmimicbidir (),
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.fbout (),
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.fref (),
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.icdrclk (),
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.pfdena (1'b1),
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.phasecounterselect ({4{1'b1}}),
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.phasedone (),
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.phasestep (1'b1),
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.phaseupdown (1'b1),
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.pllena (1'b1),
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.scanaclr (1'b0),
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.scanclk (1'b0),
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.scanclkena (1'b1),
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.scandata (1'b0),
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.scandataout (),
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.scandone (),
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.scanread (1'b0),
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.scanwrite (1'b0),
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.sclkout0 (),
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.sclkout1 (),
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.vcooverrange (),
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.vcounderrange ()
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);
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defparam
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altpll_component.bandwidth_type = "AUTO",
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altpll_component.clk0_divide_by = 1,
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altpll_component.clk0_duty_cycle = 50,
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altpll_component.clk0_multiply_by = 16,
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altpll_component.clk0_phase_shift = "0",
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altpll_component.clk1_divide_by = 1,
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altpll_component.clk1_duty_cycle = 50,
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altpll_component.clk1_multiply_by = 8,
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altpll_component.clk1_phase_shift = "2600",
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altpll_component.clk2_divide_by = 3,
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altpll_component.clk2_duty_cycle = 50,
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altpll_component.clk2_multiply_by = 16,
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altpll_component.clk2_phase_shift = "0",
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altpll_component.clk3_divide_by = 3,
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altpll_component.clk3_duty_cycle = 50,
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altpll_component.clk3_multiply_by = 8,
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altpll_component.clk3_phase_shift = "7800",
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altpll_component.clk4_divide_by = 3,
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altpll_component.clk4_duty_cycle = 50,
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altpll_component.clk4_multiply_by = 4,
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altpll_component.clk4_phase_shift = "23440",
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 83333,
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altpll_component.intended_device_family = "Cyclone 10 LP",
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altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll192",
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altpll_component.lpm_type = "altpll",
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altpll_component.operation_mode = "NORMAL",
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altpll_component.pll_type = "AUTO",
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altpll_component.port_activeclock = "PORT_UNUSED",
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altpll_component.port_areset = "PORT_UNUSED",
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altpll_component.port_clkbad0 = "PORT_UNUSED",
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altpll_component.port_clkbad1 = "PORT_UNUSED",
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altpll_component.port_clkloss = "PORT_UNUSED",
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altpll_component.port_clkswitch = "PORT_UNUSED",
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altpll_component.port_configupdate = "PORT_UNUSED",
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altpll_component.port_fbin = "PORT_UNUSED",
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altpll_component.port_inclk0 = "PORT_USED",
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altpll_component.port_inclk1 = "PORT_UNUSED",
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altpll_component.port_locked = "PORT_USED",
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altpll_component.port_pfdena = "PORT_UNUSED",
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altpll_component.port_phasecounterselect = "PORT_UNUSED",
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altpll_component.port_phasedone = "PORT_UNUSED",
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altpll_component.port_phasestep = "PORT_UNUSED",
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altpll_component.port_phaseupdown = "PORT_UNUSED",
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altpll_component.port_pllena = "PORT_UNUSED",
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altpll_component.port_scanaclr = "PORT_UNUSED",
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altpll_component.port_scanclk = "PORT_UNUSED",
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altpll_component.port_scanclkena = "PORT_UNUSED",
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altpll_component.port_scandata = "PORT_UNUSED",
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altpll_component.port_scandataout = "PORT_UNUSED",
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altpll_component.port_scandone = "PORT_UNUSED",
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altpll_component.port_scanread = "PORT_UNUSED",
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altpll_component.port_scanwrite = "PORT_UNUSED",
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altpll_component.port_clk0 = "PORT_USED",
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altpll_component.port_clk1 = "PORT_USED",
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altpll_component.port_clk2 = "PORT_USED",
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altpll_component.port_clk3 = "PORT_USED",
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altpll_component.port_clk4 = "PORT_USED",
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altpll_component.port_clk5 = "PORT_UNUSED",
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altpll_component.port_clkena0 = "PORT_UNUSED",
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altpll_component.port_clkena1 = "PORT_UNUSED",
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altpll_component.port_clkena2 = "PORT_UNUSED",
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altpll_component.port_clkena3 = "PORT_UNUSED",
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altpll_component.port_clkena4 = "PORT_UNUSED",
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altpll_component.port_clkena5 = "PORT_UNUSED",
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altpll_component.port_extclk0 = "PORT_UNUSED",
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altpll_component.port_extclk1 = "PORT_UNUSED",
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altpll_component.port_extclk2 = "PORT_UNUSED",
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altpll_component.port_extclk3 = "PORT_UNUSED",
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altpll_component.self_reset_on_loss_lock = "OFF",
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altpll_component.width_clock = 5;
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endmodule
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`else // !`ifdef PLL_LOW_LEVEL
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module pll192
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(
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input inclk0;
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output c0, c1, c2, c3, c4;
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output locked;
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);
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altpll altpll_component
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(
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.inclk ({1'b0, inclk0}),
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.clk ({c4, c3, c2, c1, c0}),
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.locked (locked),
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.activeclock (),
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.areset (1'b0),
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.clkbad (),
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.clkena ({6{1'b1}}),
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.clkloss (),
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.clkswitch (1'b0),
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.configupdate (1'b0),
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.enable0 (),
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.enable1 (),
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.extclk (),
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.extclkena ({4{1'b1}}),
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.fbin (1'b1),
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.fbmimicbidir (),
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.fbout (),
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.fref (),
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.icdrclk (),
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.pfdena (1'b1),
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.phasecounterselect ({4{1'b1}}),
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.phasedone (),
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.phasestep (1'b1),
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.phaseupdown (1'b1),
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.pllena (1'b1),
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.scanaclr (1'b0),
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.scanclk (1'b0),
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.scanclkena (1'b1),
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.scandata (1'b0),
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.scandataout (),
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.scandone (),
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.scanread (1'b0),
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.scanwrite (1'b0),
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.sclkout0 (),
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.sclkout1 (),
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.vcooverrange (),
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.vcounderrange ()
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);
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defparam
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altpll_component.charge_pump_current_bits = 1,
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 83333,
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`ifdef CYCLONE10
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altpll_component.intended_device_family = "Cyclone 10 LP",
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`endif
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altpll_component.loop_filter_c_bits = 0,
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altpll_component.loop_filter_r_bits = 24,
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altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll192",
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altpll_component.lpm_type = "altpll",
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altpll_component.m = 32,
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altpll_component.m_initial = 1,
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altpll_component.m_ph = 0,
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altpll_component.n = 1,
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altpll_component.operation_mode = "NORMAL",
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altpll_component.pll_type = "AUTO",
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altpll_component.port_activeclock = "PORT_UNUSED",
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altpll_component.port_areset = "PORT_UNUSED",
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altpll_component.port_clkbad0 = "PORT_UNUSED",
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altpll_component.port_clkbad1 = "PORT_UNUSED",
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altpll_component.port_clkloss = "PORT_UNUSED",
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altpll_component.port_clkswitch = "PORT_UNUSED",
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altpll_component.port_configupdate = "PORT_UNUSED",
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altpll_component.port_fbin = "PORT_UNUSED",
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altpll_component.port_inclk0 = "PORT_USED",
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altpll_component.port_inclk1 = "PORT_UNUSED",
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altpll_component.port_locked = "PORT_USED",
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altpll_component.port_pfdena = "PORT_UNUSED",
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altpll_component.port_phasecounterselect = "PORT_UNUSED",
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altpll_component.port_phasedone = "PORT_UNUSED",
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altpll_component.port_phasestep = "PORT_UNUSED",
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altpll_component.port_phaseupdown = "PORT_UNUSED",
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altpll_component.port_pllena = "PORT_UNUSED",
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altpll_component.port_scanaclr = "PORT_UNUSED",
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altpll_component.port_scanclk = "PORT_UNUSED",
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altpll_component.port_scanclkena = "PORT_UNUSED",
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altpll_component.port_scandata = "PORT_UNUSED",
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altpll_component.port_scandataout = "PORT_UNUSED",
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altpll_component.port_scandone = "PORT_UNUSED",
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altpll_component.port_scanread = "PORT_UNUSED",
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altpll_component.port_scanwrite = "PORT_UNUSED",
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altpll_component.port_clk0 = "PORT_USED",
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altpll_component.port_clk1 = "PORT_USED",
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altpll_component.port_clk2 = "PORT_USED",
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altpll_component.port_clk3 = "PORT_USED",
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altpll_component.port_clk4 = "PORT_USED",
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altpll_component.port_clk5 = "PORT_UNUSED",
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altpll_component.port_clkena0 = "PORT_UNUSED",
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altpll_component.port_clkena1 = "PORT_UNUSED",
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altpll_component.port_clkena2 = "PORT_UNUSED",
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altpll_component.port_clkena3 = "PORT_UNUSED",
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altpll_component.port_clkena4 = "PORT_UNUSED",
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altpll_component.port_clkena5 = "PORT_UNUSED",
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altpll_component.port_extclk0 = "PORT_UNUSED",
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altpll_component.port_extclk1 = "PORT_UNUSED",
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altpll_component.port_extclk2 = "PORT_UNUSED",
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altpll_component.port_extclk3 = "PORT_UNUSED",
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altpll_component.self_reset_on_loss_lock = "OFF",
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altpll_component.vco_post_scale = 2,
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altpll_component.width_clock = 5,
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altpll_component.c0_high = 1,
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altpll_component.c0_initial = 1,
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altpll_component.c0_low = 1,
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altpll_component.c0_mode = "even",
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altpll_component.c0_ph = 0,
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altpll_component.c1_high = 2,
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altpll_component.c1_initial = 2,
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altpll_component.c1_low = 2,
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altpll_component.c1_mode = "even",
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altpll_component.c1_ph = 0,
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altpll_component.c2_high = 3,
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altpll_component.c2_initial = 1,
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altpll_component.c2_low = 3,
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altpll_component.c2_mode = "even",
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altpll_component.c2_ph = 0,
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altpll_component.c3_high = 6,
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altpll_component.c3_initial = 4,
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altpll_component.c3_low = 6,
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altpll_component.c3_mode = "even",
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altpll_component.c3_ph = 0,
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altpll_component.c4_high = 12,
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altpll_component.c4_initial = 10,
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altpll_component.c4_low = 12,
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altpll_component.c4_mode = "even",
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altpll_component.c4_ph = 0,
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altpll_component.clk0_counter = "c0",
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altpll_component.clk1_counter = "c1",
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altpll_component.clk2_counter = "c2",
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altpll_component.clk3_counter = "c3",
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altpll_component.clk4_counter = "c4";
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endmodule
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`endif // !`ifdef PLL_LOW_LEVEL
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`endif // !`ifdef SIMULATION
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