Exact

Exact Union RegExp

Stephan I. Böttcher 9c9d89f454 altera synthesis of empty design succeeds		2025-12-22 00:02:43 +01:00
..
Makefile	altera synthesis of empty design succeeds	2025-12-22 00:02:43 +01:00
pll.v	altera synthesis of empty design succeeds	2025-12-22 00:02:43 +01:00
thhor_crs.qpf	fpga pinout, with fixes on the schematics and layout	2025-12-21 23:27:15 +01:00
thhor_crs.qsf	altera synthesis of empty design succeeds	2025-12-22 00:02:43 +01:00
thhor_crs.sdc	altera synthesis of empty design succeeds	2025-12-22 00:02:43 +01:00
thhor_crs.v	altera synthesis of empty design succeeds	2025-12-22 00:02:43 +01:00
thhor_crs.warnings	altera synthesis of empty design succeeds	2025-12-22 00:02:43 +01:00