thhor_crs/fpga/thhor_crs.v
2025-12-22 00:02:43 +01:00

38 lines
618 B
Verilog

module thhor_crs
(
input xclk,
input spi_ssel, spi_sck, spi_mosi,
output spi_miso,
// Barometer
output pt_MCLK, pt_SCLK, pt_Din,
input pt_Dout,
// ADCs
output [3:0] ADC_nCS, ADC_SCK, ADC_DIN,
input [3:0] ADC_DOUT,
// LVDS
output S_OUT, D_OUT,
input S_IN, D_IN,
// Spare Pins
inout [18:0] P25,
inout [7:0] P33
);
wire pll_locked;
wire mclk;
pll192 pll(.inclk0(xclk),
.c3(mclk),
.locked(pll_locked)
);
reg r;
assign spi_miso = r;
always @(posedge mclk)
if (spi_ssel)
r <= spi_mosi;
endmodule // thhor_crs