thhor_crs/fpga/thhor_crs.sdc
2025-12-22 00:02:43 +01:00

7 lines
331 B
Tcl

create_clock -name xclk -period 83.333 xclk
derive_pll_clocks
derive_clock_uncertainty
set_false_path -from spi_sck -to xclk
set_false_path -from xclk -to spi_sck
set_false_path -from spi_sck -to {pll|altpll_component|auto_generated|pll1|clk[3]}
set_false_path -from {pll|altpll_component|auto_generated|pll1|clk[3]} -to spi_sck