thhor_crs/fpga/thhor_crs.sdc

create_clock -name xclk -period 83.333 xclk
derive_pll_clocks
derive_clock_uncertainty
set_false_path -from spi_sck -to xclk
set_false_path -from xclk -to  spi_sck
set_false_path -from spi_sck -to  {pll|altpll_component|auto_generated|pll1|clk[3]}
set_false_path -from {pll|altpll_component|auto_generated|pll1|clk[3]} -to spi_sck
fpga pinout, with fixes on the schematics and layout 2025-12-21 23:27:15 +01:00			`create_clock -name xclk -period 83.333 xclk`
fpga: nmrena unmodified 2025-12-21 21:40:54 +01:00			`derive_pll_clocks`
			`derive_clock_uncertainty`
fpga pinout, with fixes on the schematics and layout 2025-12-21 23:27:15 +01:00			`set_false_path -from spi_sck -to xclk`
			`set_false_path -from xclk -to spi_sck`
altera synthesis of empty design succeeds 2025-12-22 00:02:43 +01:00			`set_false_path -from spi_sck -to {pll\|altpll_component\|auto_generated\|pll1\|clk[3]}`
			`set_false_path -from {pll\|altpll_component\|auto_generated\|pll1\|clk[3]} -to spi_sck`