42 lines
1.1 KiB
Makefile
42 lines
1.1 KiB
Makefile
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VERILOG=/usr/bin/iverilog
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VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
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%.vvp:
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$(VERILOG) $(VERILOGFLAGS) $(VFLAGS) -o $@ $^
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vcd/%.fst: %.vvp
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$< -fst | tee $*.log
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.PRECIOUS: vcd/%.fst
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THHOR_CRS_SRC = thhor_crs.v pll.v
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thhor_crs.vvp: $(THHOR_CRS_SRC)
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thhor_crs_FLAGS = -sthhor_crs_test -DTHHOR_CRS -DTHHOR_CRS_TEST
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CYCLONE=10
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ifeq ($(CYCLONE),10)
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QUARTUS=/usr/local/quartus/intelFPGA_lite/20.1/quartus
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else
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QUARTUS=/usr/local/quartus/altera13.1/quartus
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endif
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export PATH:=$(QUARTUS)/bin:$(PATH):.
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MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS) $(MAPDEFS))
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QDIR=quartus
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$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
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quartus_map $< $(MAPFLGS)
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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grep -i warning $(QDIR)/$*.*.rpt \
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| grep -v 'behaves as a Local Parameter Declaration because the module' \
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| grep -v 'truncated value with size 32 to match size of target' \
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| sed 's/\.v([0-9]\+)/.v(…)/;s/File: .* Line: [0-9]\+$$//' \
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> $*.warnings
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grep '^; -' $(QDIR)/$*.sta.rpt >> $*.warnings || echo Timing OK
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$(QDIR)/thhor_crs.rbf: thhor_crs.v pll.v
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