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thhor_crs/fpga
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Stephan I. Böttcher 3f9a100e7c fpga spi_slave: longer sclk timeout 
The µC needs about 5 µs between bytes.  The 128 mclk timeout @32MHz is
4.3µs.  This commit extends the timeout to 1024 mclk cycles.
2026-03-25 20:20:07 +01:00
..
solo@9bbfeb3316 fpga spi_slave: longer sclk timeout 2026-03-25 20:20:07 +01:00
Makefile fpga/Makefile: iverilog v14 2026-03-18 20:55:59 +01:00
pll.v altera synthesis of empty design succeeds 2025-12-22 00:02:43 +01:00
thhor_crs.gold stis_slice, nm_counters, pressure, ax_port 2026-03-16 08:22:49 +01:00
thhor_crs.qpf fpga pinout, with fixes on the schematics and layout 2025-12-21 23:27:15 +01:00
thhor_crs.qsf fpga spi_slave: longer sclk timeout 2026-03-25 20:20:07 +01:00
thhor_crs.sdc stis_slice, nm_counters, pressure, ax_port 2026-03-16 08:22:49 +01:00
thhor_crs.v move net delc before use 2026-03-16 22:26:27 +01:00
thhor_crs.warnings fpga spi_slave: longer sclk timeout 2026-03-25 20:20:07 +01:00