58 lines
1.9 KiB
Makefile
58 lines
1.9 KiB
Makefile
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VERILOG=iverilog -gno-strict-parameter-declaration -Wno-declaration-after-use
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VERILOGFLAGS = -v -DSIMULATION $($*_FLAGS)
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%.vvp:
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$(VERILOG) $(VERILOGFLAGS) $(VFLAGS) -o $@ $^
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vcd/%.fst: %.vvp
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$< -fst | tee $*.log
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.PRECIOUS: vcd/%.fst
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VPATH = solo/altera : solo/irena/altera: solo/irena/altera/adc128: \
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solo/dorn/altera : solo/nm64/altera
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FRONTEND_FILES = frontend_test.v spi_slave.v frontend.v packetfifo.v conf_reg.v spififo_sim.v \
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countbits.v serializer.v secondcyclone.v
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DORN_FILES = thhor_core.v stis_ana_core.v dorn.v multiply.v divider.v nmcounter.v dmem.v
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IRENA_FILES = frontend_test.v mem.v itof.v ms5540c.v adc128s102.v pulser.v
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THHOR_CRS_SRC = thhor_crs.v $(FRONTEND_FILES) $(DORN_FILES) $(IRENA_FILES)
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thhor_crs.vvp: $(THHOR_CRS_SRC)
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vcd/thhor_crs.fst: sallen-key-pulse.hex
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sallen-key-pulse.hex:
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ln -f solo/dorn/altera/$@
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DORN_FLAGS = -DWITH_FULL_L1_CONF -DWITH_FULL_L2_CONF -DWITH_FULL_L3_CONF \
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-DANA_WITHOUT_SERIALIZER -DSPARSE_TRIG_EN -DL2_AHEPAM
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ARCH_FLAGS = -DSTIS_ANA_JIG -DINFERRED_SRAM -DSER_FIFO_ALTERA -DWITH_SPI_SSEL
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thhor_crs_FLAGS = -sthhor_crs_test -DTHHOR -DTHHOR_CRS_TEST -DAX_PORT \
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$(DORN_FLAGS) $(ARCH_FLAGS)
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CYCLONE=10
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ifeq ($(CYCLONE),10)
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QUARTUS=/usr/local/quartus/intelFPGA_lite/20.1/quartus
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else
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QUARTUS=/usr/local/quartus/altera13.1/quartus
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endif
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export PATH:=$(QUARTUS)/bin:$(PATH):.
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MAPFLGS = $(patsubst %, --verilog_macro="%",$($*_MAPDEFS) $(MAPDEFS))
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QDIR=quartus
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$(QDIR)/%.rbf: %.qpf %.qsf %.sdc
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quartus_map $< $(MAPFLGS)
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quartus_fit $<
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quartus_asm $<
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quartus_sta $<
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grep -i warning $(QDIR)/$*.*.rpt \
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| grep -v 'behaves as a Local Parameter Declaration because the module' \
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| grep -v 'truncated value with size 32 to match size of target' \
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| sed 's/\.v([0-9]\+)/.v(…)/;s/File: .* Line: [0-9]\+$$//' \
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> $*.warnings
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grep '^; -' $(QDIR)/$*.sta.rpt >> $*.warnings || echo Timing OK
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$(QDIR)/thhor_crs.rbf: thhor_crs.v pll.v
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